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R. Govindarajan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Madhavi Gopal Valluri, R. Govindarajan
    Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:78-83 [Conf]
  2. R. Vinodh Kumar, B. Lakshmi Narayanan, R. Govindarajan
    Dynamic Path Profile Aided Recompilation in a JAVA Just-In-Time Compiler. [Citation Graph (0, 0)][DBLP]
    HiPC, 2002, pp:495-505 [Conf]
  3. A. Radhika Sarma, R. Govindarajan
    An Efficient Web Cache Replacement Policy. [Citation Graph (0, 0)][DBLP]
    HiPC, 2003, pp:12-22 [Conf]
  4. K. V. Manjunath, R. Govindarajan
    Hidden Costs in Avoiding False Sharing in Software DSMs. [Citation Graph (0, 0)][DBLP]
    HiPC, 2001, pp:294-306 [Conf]
  5. V. Santhosh Kumar, Matthew J. Thazhuthaveetil, R. Govindarajan
    Offloading Bloom Filter Operations to Network Processor for Parallel Query Processing in Cluster of Workstations. [Citation Graph (0, 0)][DBLP]
    HiPC, 2005, pp:170-179 [Conf]
  6. Subash G. Chandar, Mahesh Mehendale, R. Govindarajan
    Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:631-634 [Conf]
  7. S. Ramesh, R. Lakshmi, R. Govindarajan
    Distributed Shared Memory on IBM SP2. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1997, pp:338-345 [Conf]
  8. Rajesh Vivekanandham, Bharadwaj Amrutur, R. Govindarajan
    A scalable low power issue queue for large instruction window processors. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:167-176 [Conf]
  9. R. Achutharaman, R. Govindarajan, G. Hariprakash, Amos Omondi
    Exploiting Java-ILP on a Simultaneous Multi-Trace Instruction Issue (SMTI) Processor. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:76- [Conf]
  10. V. Santhosh Kumar, Matthew J. Thazhuthaveetil, R. Govindarajan
    Exploiting programmable network interfaces for parallel query execution in workstation clusters. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  11. R. Govindarajan, Sheng Yu
    Data Flow Implementation of Generalized Guarded Commands. [Citation Graph (0, 0)][DBLP]
    PARLE (1), 1991, pp:372-389 [Conf]
  12. S. Govind, R. Govindarajan
    Performance Modeling and Architecture Exploration of Network Processors. [Citation Graph (0, 0)][DBLP]
    QEST, 2005, pp:189-198 [Conf]
  13. V. V. N. S. Sarvani, R. Govindarajan
    Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:270-284 [Conf]
  14. T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravi Kumar
    Optimal Code and Data Layout in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:573-578 [Conf]
  15. T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan
    MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:527-533 [Conf]
  16. R. Govindarajan, Lalit M. Patnaik
    Lenient Execution and Concurrent Execution of Re-Entrant Routines: Efficient Implementation in Data Flow Systems. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1990, v:33, n:2, pp:185-187 [Journal]
  17. N. P. Manoj, K. V. Manjunath, R. Govindarajan
    CAS-DSM: A Compiler Assisted Software Distributed Shared Memory. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2004, v:32, n:2, pp:77-122 [Journal]
  18. N. Sreraman, R. Govindarajan
    A Vectorizing Compiler for Multimedia Extensions. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2000, v:28, n:4, pp:363-400 [Journal]
  19. Manjunath Kudlur, R. Govindarajan
    Performance analysis of methods that overcome false sharing effects in software DSMs. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2004, v:64, n:8, pp:887-907 [Journal]
  20. Lalit M. Patnaik, R. Govindarajan, N. S. Ramadoss
    Design and Performance Evaluation of EXMAN: An EXtended MANchester Data Flow Computer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:3, pp:229-244 [Journal]
  21. R. Govindarajan
    Exception Handlers in Functional Programming Languages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1993, v:19, n:8, pp:826-834 [Journal]
  22. Santosh G. Nagarakatte, R. Govindarajan
    Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming Formulation. [Citation Graph (0, 0)][DBLP]
    CC, 2007, pp:126-140 [Conf]
  23. K. Shyam, R. Govindarajan
    An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures. [Citation Graph (0, 0)][DBLP]
    CC, 2007, pp:32-47 [Conf]
  24. S. Govind, R. Govindarajan, Joy Kuri
    Packet Reordering in Network Processors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-10 [Conf]
  25. Rajani Pai, R. Govindarajan
    FEADS: A Framework for Exploring the Application Design Space on Network Processors. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2007, v:35, n:1, pp:1-31 [Journal]
  26. Subash G. Chandar, Mahesh Mehendale, R. Govindarajan
    Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:3, pp:245-267 [Journal]

  27. A Scalable Low Power Store Queue for Large InstructionWindow Processors. [Citation Graph (, )][DBLP]

  28. MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip. [Citation Graph (, )][DBLP]

  29. Software Pipelined Execution of Stream Programs on GPUs. [Citation Graph (, )][DBLP]

  30. Comprehensive path-sensitive data-flow analysis. [Citation Graph (, )][DBLP]

  31. Compiler-Directed Dynamic Voltage Scaling Using Program Phases. [Citation Graph (, )][DBLP]

  32. Focused prefetching: performance oriented prefetching based on commit stalls. [Citation Graph (, )][DBLP]

  33. Synergistic execution of stream programs on multicores with accelerators. [Citation Graph (, )][DBLP]

  34. A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor. [Citation Graph (, )][DBLP]

  35. Memory Architecture Exploration Framework for Cache Based Embedded SOC. [Citation Graph (, )][DBLP]

  36. A systematic approach to synthesis of verification test-suites for modular SoC designs. [Citation Graph (, )][DBLP]

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