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Publications of Author

1. Roni Rosner, Avi Mendelson, Ronny Ronen
   Filtering Techniques to Improve Trace-Cache Efficiency. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2001, pp:37-48 [Conf]
   
2. Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen
   eXtended Block Cache. [Citation Graph (0, 0)][DBLP]
   HPCA, 2000, pp:61-0 [Conf]
   
3. Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang
   Best of Both Latency and Throughput. [Citation Graph (0, 0)][DBLP]
   ICCD, 2004, pp:236-243 [Conf]
   
4. Roni Rosner, Micha Moffie, Yiannakis Sazeides, Ronny Ronen
   Selecting long atomic traces for high coverage. [Citation Graph (0, 0)][DBLP]
   ICS, 2003, pp:2-11 [Conf]
   
5. Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stéphan Jourdan, Maxim Kalaev, Ronny Ronen
   Early load address resolution via register tracking. [Citation Graph (0, 0)][DBLP]
   ISCA, 2000, pp:306-315 [Conf]
   
6. Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri Weiser
   Correlated Load-Address Predictors. [Citation Graph (0, 0)][DBLP]
   ISCA, 1999, pp:54-63 [Conf]
   
7. Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan Jourdan
   Speculation Techniques for Improving Load Related Instruction Scheduling. [Citation Graph (0, 0)][DBLP]
   ISCA, 1999, pp:42-53 [Conf]
   
8. Baruch Solomon, Avi Mendelson, Doron Orenstein, Yoav Almog, Ronny Ronen
   Micro-operation cache: a power aware frontend for the variable instruction length ISA. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2001, pp:4-9 [Conf]
   
9. Stéphan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz
   A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification. [Citation Graph (0, 0)][DBLP]
   MICRO, 1998, pp:216-225 [Conf]
   
10. Aviad Cohen, Lev Finkelstein, Avi Mendelson, Ronny Ronen, Dmitry Rudoy
    On Estimating Optimal Performance of CPU Dynamic Thermal Management. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2003, v:2, n:, pp:- [Journal]
    
11. Ronny Ronen, Antonio González
    Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:8-11 [Journal]
    
12. Baruch Solomon, Avi Mendelson, Ronny Ronen, Doron Orenstein, Yoav Almog
    Micro-operation cache: a power aware frontend for variable instruction length ISA. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:801-811 [Journal]
    
13. 
    Larrabee: a many-core Intel architecture for visual computing. [Citation Graph (, )][DBLP]
    
    
14. 
    Terascale chip multiprocessor memory hierarchy and programming model. [Citation Graph (, )][DBLP]
    
    
15. 
    Programming model for a heterogeneous x86 platform. [Citation Graph (, )][DBLP]