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Mark D. Hill: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sarita V. Adve, Mark D. Hill
    Weak Ordering - A New Definition. [Citation Graph (1, 0)][DBLP]
    ISCA, 1990, pp:2-14 [Conf]
  2. Trishul M. Chilimbi, Mark D. Hill, James R. Larus
    Cache-Conscious Structure Layout. [Citation Graph (1, 0)][DBLP]
    PLDI, 1999, pp:1-12 [Conf]
  3. Anastassia Ailamaki, David J. DeWitt, Mark D. Hill, David A. Wood
    DBMSs on a Modern Processor: Where Does Time Go? [Citation Graph (1, 14)][DBLP]
    VLDB, 1999, pp:266-277 [Conf]
  4. Mark D. Hill, Alan Jay Smith
    Evaluating Associativity in CPU Caches. [Citation Graph (1, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:12, pp:1612-1630 [Journal]
  5. Mark D. Hill, James R. Larus, Steven K. Reinhardt, David A. Wood
    Cooperative Shared Memory: Software and Hardware Support for Scalable Multiprocesors. [Citation Graph (1, 0)][DBLP]
    ACM Trans. Comput. Syst., 1993, v:11, n:4, pp:300-318 [Journal]
  6. Richard E. Kessler, Mark D. Hill
    Page Placement Algorithms for Large Real-Indexed Caches. [Citation Graph (1, 0)][DBLP]
    ACM Trans. Comput. Syst., 1992, v:10, n:4, pp:338-359 [Journal]
  7. Ioannis Schoinas, Babak Falsafi, Mark D. Hill, James R. Larus, David A. Wood
    Sirocco: Cost-Effective Fine-Grain Distributed Shared Memory. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:40-0 [Conf]
  8. Mark D. Hill, James R. Larus, Steven K. Reinhardt, David A. Wood
    Cooperative Shared Memory: Software and Hardware Support for Scalable Multiprocesors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1992, pp:262-273 [Conf]
  9. Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, David A. Wood
    Timestamp snooping: an approach for extending SMPs. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2000, pp:25-36 [Conf]
  10. Madhusudhan Talluri, Mark D. Hill
    Surpassing the TLB Performance of Superpages with Less Operating System Support. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1994, pp:171-182 [Conf]
  11. Min Xu, Mark D. Hill, Rastislav Bodík
    A regulated transitive reduction (RTR) for longer memory race recording. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:49-60 [Conf]
  12. Michelle J. Moravan, Jayaram Bobba, Kevin E. Moore, Luke Yen, Mark D. Hill, Ben Liblit, Michael M. Swift, David A. Wood
    Supporting nested transactional memory in logTM. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:359-370 [Conf]
  13. Mark D. Hill, James R. Larus, David A. Wood
    Tempest: A Substrate for Portable Parallel Programs. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1995, pp:327-332 [Conf]
  14. Daniel J. Sorin, Mark D. Hill, David A. Wood
    Dynamic Verification of End-to-End Multiprocessor Invariants. [Citation Graph (0, 0)][DBLP]
    DSN, 2003, pp:281-290 [Conf]
  15. Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J. Sorin
    Using Lamport Clocks to Reason about Relaxed Memory Models. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:270-278 [Conf]
  16. Shubhendu S. Mukherjee, Mark D. Hill
    The Impact of Data Transfer and Buffering Alternatives on Network Interface Design. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:207-218 [Conf]
  17. Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, David A. Wood
    Bandwidth Adaptive Snooping. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:251-262 [Conf]
  18. Michael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M. K. Martin, David A. Wood
    Improving Multiple-CMP Systems Using Token Coherence. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:328-339 [Conf]
  19. Ioannis Schoinas, Mark D. Hill
    Address Translation Mechanisms In Network Interfaces. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:219-230 [Conf]
  20. David A. Wood, Mark D. Hill, James R. Larus
    The Tempest approach to distributed shared memory. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:63-0 [Conf]
  21. Sarita V. Adve, Mark D. Hill
    Implementing Sequential Consistency in Cache-Based Systems. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:47-50 [Conf]
  22. Mark D. Hill
    A Future of Parallel Computer Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP, 2004, pp:2- [Conf]
  23. Shubhendu S. Mukherjee, Mark D. Hill
    An evaluation of directory protocols for medium-scale shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1994, pp:64-74 [Conf]
  24. Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood
    Using Speculation to Simplify Multiprocessor Design. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  25. Sarita V. Adve, Vikram S. Adve, Mark D. Hill, Mary K. Vernon
    Comparison of Hardware and Software Cache Coherence Schemes. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:298-308 [Conf]
  26. Sarita V. Adve, Mark D. Hill
    Retrospective: Weak Ordering - A New Definition. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:63-66 [Conf]
  27. Sarita V. Adve, Mark D. Hill
    Weak Ordering - A New Definition. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:363-375 [Conf]
  28. Sarita V. Adve, Mark D. Hill, Barton P. Miller, Robert H. B. Netzer
    Detecting Data Races on Weak Memory Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:234-243 [Conf]
  29. E. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, David A. Wood
    Multicast Snooping: A New Coherence Method Using a Multicast Address Network. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:294-304 [Conf]
  30. Brian A. Fields, Rastislav Bodík, Mark D. Hill
    Slack: Maximizing Performance Under Technological Constraints. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:47-58 [Conf]
  31. Mark D. Hill, Alan Jay Smith
    Experimental Evaluation of On-Chip Microprocessor Cache Memories. [Citation Graph (0, 0)][DBLP]
    ISCA, 1984, pp:158-166 [Conf]
  32. Richard E. Kessler, Richard Jooss, Alvin R. Lebeck, Mark D. Hill
    Inexpensive Implementations of Set-Associativity. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:131-139 [Conf]
  33. Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, David A. Wood
    Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:206-217 [Conf]
  34. Milo M. K. Martin, Mark D. Hill, David A. Wood
    Token Coherence: Decoupling Performance and Correctness. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:182-193 [Conf]
  35. Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hill, David A. Wood
    Coherent Network Interfaces for Fine-Grain Communication. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:247-258 [Conf]
  36. Shubhendu S. Mukherjee, Mark D. Hill
    Using Prediction to Accelerate Coherence Protocols. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:179-190 [Conf]
  37. David A. Patterson, Phil Garrison, Mark D. Hill, Dimitris Lioupis, Chris Nyberg, Tim Sippel, Korbin Van Dyke
    Architecture of a VLSI Instruction Cache for a RISC [Citation Graph (0, 0)][DBLP]
    ISCA, 1983, pp:108-116 [Conf]
  38. Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood
    SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:123-0 [Conf]
  39. Madhusudhan Talluri, Shing I. Kong, Mark D. Hill, David A. Patterson
    Tradeoffs in Supporting Two Page Sizes. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:415-424 [Conf]
  40. David A. Wood, Satish Chandra, Babak Falsafi, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, Shubhendu S. Mukherjee, Subbarao Palacharla, Steven K. Reinhardt
    Mechanisms for Cooperative Shared Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:156-167 [Conf]
  41. David A. Wood, Susan J. Eggers, Garth A. Gibson, Mark D. Hill, Joan M. Pendleton, Scott A. Ritchie, George S. Taylor, Randy H. Katz, David A. Patterson
    An In-Cache Address Translation Mechanism. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:358-365 [Conf]
  42. Min Xu, Rastislav Bodík, Mark D. Hill
    A "Flight Data Recorder" for Enabling Full-System Multiprocessor Deterministic Replay. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:122-133 [Conf]
  43. Brian A. Fields, Rastislav Bodík, Mark D. Hill, Chris J. Newburn
    Using Interaction Costs for Microarchitectural Bottleneck Analysis. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:228-242 [Conf]
  44. Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, Mikko H. Lipasti
    Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:328-337 [Conf]
  45. Michael R. Marty, Mark D. Hill
    Coherence Ordering for Ring-based Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:309-320 [Conf]
  46. Sashikanth Chandrasekaran, Mark D. Hill
    Optimistic Simulation of Parallel Architectures Using Program Executables. [Citation Graph (0, 0)][DBLP]
    Workshop on Parallel and Distributed Simulation, 1996, pp:143-150 [Conf]
  47. Eric Schnarr, Mark D. Hill, James R. Larus
    Facile: A Language and Compiler for High-Performance Processor Simulators. [Citation Graph (0, 0)][DBLP]
    PLDI, 2001, pp:321-331 [Conf]
  48. Min Xu, Rastislav Bodík, Mark D. Hill
    A serializability violation detector for shared-memory server programs. [Citation Graph (0, 0)][DBLP]
    PLDI, 2005, pp:1-14 [Conf]
  49. Mark D. Hill
    How computer architecture trends may affect future distributed systems: from infiniBand clusters to inter-processor speculation (abstract). [Citation Graph (0, 0)][DBLP]
    PODC, 2000, pp:6- [Conf]
  50. Shubhendu S. Mukherjee, Shamik D. Sharma, Mark D. Hill, James R. Larus, Anne Rogers, Joel H. Saltz
    Efficient Support for Irregular Applications on Distributed-Memory Machines. [Citation Graph (0, 0)][DBLP]
    PPOPP, 1995, pp:68-79 [Conf]
  51. Yuanyuan Zhou, Liviu Iftode, Jaswinder Pal Singh, Kai Li, Brian R. Toonen, Ioannis Schoinas, Mark D. Hill, David A. Wood
    Relaxed Consistency and Coherence Granularity in DSM Systems: A Performance Evaluation. [Citation Graph (0, 0)][DBLP]
    PPOPP, 1997, pp:193-205 [Conf]
  52. Babak Falsafi, Alvin R. Lebeck, Steven K. Reinhardt, Ioannis Schoinas, Mark D. Hill, James R. Larus, Anne Rogers, David A. Wood
    Application-specific protocols for user-level shared memory. [Citation Graph (0, 0)][DBLP]
    SC, 1994, pp:380-389 [Conf]
  53. Yul H. Kim, Mark D. Hill, David A. Wood
    Implementing Stack Simulation for Highly-Associative Memories. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1991, pp:212-213 [Conf]
  54. Carl J. Mauer, Mark D. Hill, David A. Wood
    Full-system timing-first simulation. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2002, pp:108-116 [Conf]
  55. Steven K. Reinhardt, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, David A. Wood
    The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1993, pp:48-60 [Conf]
  56. David A. Wood, Mark D. Hill, Richard E. Kessler
    A Model for Estimating Trace-Sample Miss Ratios. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1991, pp:79-89 [Conf]
  57. Madhusudhan Talluri, Mark D. Hill, Yousef Y. A. Khalidi
    A New Page Table for 64-bit Address Spaces. [Citation Graph (0, 0)][DBLP]
    SOSP, 1995, pp:184-200 [Conf]
  58. Mark D. Hill, Anne Condon, Manoj Plakal, Daniel J. Sorin
    A System-Level Specification Framework for I/O Architectures. [Citation Graph (0, 0)][DBLP]
    SPAA, 1999, pp:138-147 [Conf]
  59. Manoj Plakal, Daniel J. Sorin, Anne Condon, Mark D. Hill
    Lamport Clocks: Verifying a Directory Cache-Coherence Protocol. [Citation Graph (0, 0)][DBLP]
    SPAA, 1998, pp:67-76 [Conf]
  60. Anastassia Ailamaki, David J. DeWitt, Mark D. Hill, Marios Skounakis
    Weaving Relations for Cache Performance. [Citation Graph (0, 0)][DBLP]
    VLDB, 2001, pp:169-180 [Conf]
  61. Mark D. Hill, James R. Larus
    Cache Considerations for Multiprocessor Programmers. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1990, v:33, n:8, pp:97-102 [Journal]
  62. Mark D. Hill, Jean-Luc Gaudiot, Mary W. Hall, Joe Marks, Paolo Prinetto, Donna Baglio
    A Wiki for discussing and promoting best practices in research. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 2006, v:49, n:9, pp:63-64 [Journal]
  63. Alaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Mark D. Hill, David A. Wood, Daniel J. Sorin
    Simulating a $2M Commercial Server on a $2K PC. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:2, pp:50-57 [Journal]
  64. Andrew A. Chien, Mark D. Hill, Shubhendu S. Mukherjee
    Design Challenges for High-Performance Network Interfaces - Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1998, v:31, n:11, pp:42-44 [Journal]
  65. Trishul M. Chilimbi, Mark D. Hill, James R. Larus
    Making Pointer-Based Data Structures Cache Conscious. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2000, v:33, n:12, pp:67-74 [Journal]
  66. Mark D. Hill
    A Case for Direct-Mapped Caches. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1988, v:21, n:12, pp:25-40 [Journal]
  67. Mark D. Hill
    Multiprocessors Should Support Simple Memory-Consistency Models. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1998, v:31, n:8, pp:28-34 [Journal]
  68. Ted G. Lewis, Dave Power, Bertrand Meyer, Jack Grimes, Mike Potel, Ronald J. Vetter, Phillip A. Laplante, Wolfgang Pree, Gustav Pomberger, Mark D. Hill, James R. Larus, David A. Wood, Hesham El-Rewini, Bruce W. Weide
    Where Is Software Headed? A Virtual Roundtable. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1995, v:28, n:8, pp:20-32 [Journal]
  69. Shubhendu S. Mukherjee, Mark D. Hill
    Making Network Interfaces Less Peripheral. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1998, v:31, n:10, pp:70-76 [Journal]
  70. Kevin Skadron, Margaret Martonosi, David I. August, Mark D. Hill, David J. Lilja, Vijay S. Pai
    Challenges in Computer Architecture Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:8, pp:30-36 [Journal]
  71. David A. Wood, Mark D. Hill
    Cost-Effective Parallel Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1995, v:28, n:2, pp:69-72 [Journal]
  72. Kourosh Gharachorloo, Sarita V. Adve, Anoop Gupta, John L. Hennessy, Mark D. Hill
    Programming for Different Memory Consistency Models. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1992, v:15, n:4, pp:399-407 [Journal]
  73. Brian A. Fields, Rastislav Bodík, Mark D. Hill, Chris J. Newburn
    Interaction Cost: For When Event Counts Just Don't Add Up. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:57-61 [Journal]
  74. Milo M. K. Martin, Mark D. Hill, David A. Wood
    Token Coherence: A New Framework for Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:108-116 [Journal]
  75. Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, David A. Wood
    Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:4, pp:92-99 [Journal]
  76. Jason F. Cantin, Mark D. Hill
    Cache performance for selected SPEC CPU2000 benchmarks. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2001, v:29, n:4, pp:13-18 [Journal]
  77. Brian A. Fields, Rastislav Bodík, Mark D. Hill, Chris J. Newburn
    Interaction cost and shotgun profiling. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:3, pp:272-304 [Journal]
  78. Richard E. Kessler, Mark D. Hill, David A. Wood
    A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:6, pp:664-675 [Journal]
  79. Andreas Farid Pour, Mark D. Hill
    Performance Implications of Tolerating Cache Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:3, pp:257-267 [Journal]
  80. Sarita V. Adve, Mark D. Hill
    A Unified Formalization of Four Shared-Memory Models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:6, pp:613-624 [Journal]
  81. Daniel J. Sorin, Manoj Plakal, Anne Condon, Mark D. Hill, Milo M. K. Martin, David A. Wood
    Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2002, v:13, n:6, pp:556-578 [Journal]
  82. Anastassia Ailamaki, David J. DeWitt, Mark D. Hill
    Data page layouts for relational databases on deep memory hierarchies. [Citation Graph (0, 0)][DBLP]
    VLDB J., 2002, v:11, n:3, pp:198-215 [Journal]
  83. Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, David A. Wood
    Performance pathologies in hardware transactional memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:81-91 [Conf]
  84. Michael R. Marty, Mark D. Hill
    Virtual hierarchies to support server consolidation. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:46-56 [Conf]
  85. Min Xu, Rastislav Bodík, Mark D. Hill
    A Hardware Memory Race Recorder for Deterministic Replay. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:48-55 [Journal]

  86. StealthTest: Low Overhead Online Software Testing Using Transactional Memory. [Citation Graph (, )][DBLP]


  87. A Case for Deconstructing Hardware Transactional Memory Systems. [Citation Graph (, )][DBLP]


  88. LogTM-SE: Decoupling Hardware Transactional Memory from Caches. [Citation Graph (, )][DBLP]


  89. LogTM: log-based transactional memory. [Citation Graph (, )][DBLP]


  90. Amdahl's Law in the multicore era. [Citation Graph (, )][DBLP]


  91. Opportunities beyond single-core microprocessors. [Citation Graph (, )][DBLP]


  92. TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory. [Citation Graph (, )][DBLP]


  93. Rerun: Exploiting Episodes for Lightweight Memory Race Recording. [Citation Graph (, )][DBLP]


  94. Implementing Signatures for Transactional Memory. [Citation Graph (, )][DBLP]


  95. Notary: Hardware techniques to enhance signatures. [Citation Graph (, )][DBLP]


  96. Opportunities beyond single-core microprocessors. [Citation Graph (, )][DBLP]


  97. Two hardware-based approaches for deterministic multiprocessor replay. [Citation Graph (, )][DBLP]


  98. Amdahl's Law in the Multicore Era. [Citation Graph (, )][DBLP]


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