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Ali-Reza Adl-Tabatabai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tatiana Shpeisman, Guei-Yuan Lueh, Ali-Reza Adl-Tabatabai
    Just-In-Time Java? Compilation for the Itanium® Processor. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:249-258 [Conf]
  2. Ali-Reza Adl-Tabatabai, Jay Bharadwaj, Michal Cierniak, Marsha Eng, Jesse Fang, Brian T. Lewis, Brian R. Murphy, James M. Stichnoth
    Improving 64-Bit Java IPF Performance by Compressing Heap References. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:100-110 [Conf]
  3. Cheng Wang, Wei-Yu Chen, Youfeng Wu, Bratin Saha, Ali-Reza Adl-Tabatabai
    Code Generation and Optimization for Transactional Memory Constructs in an Unmanaged Language. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:34-48 [Conf]
  4. Ali-Reza Adl-Tabatabai, Thomas R. Gross, Guei-Yuan Lueh, James Reinders
    Modeling Instruction-Level Parallelism for Software Pipelining. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:321-330 [Conf]
  5. Richard L. Hudson, Bratin Saha, Ali-Reza Adl-Tabatabai, Ben Hertzberg
    McRT-Malloc: a scalable transactional memory allocator. [Citation Graph (0, 0)][DBLP]
    ISMM, 2006, pp:74-83 [Conf]
  6. Guei-Yuan Lueh, Thomas R. Gross, Ali-Reza Adl-Tabatabai
    Global Register Allocation Based on Graph Fusion. [Citation Graph (0, 0)][DBLP]
    LCPC, 1996, pp:246-265 [Conf]
  7. Bratin Saha, Ali-Reza Adl-Tabatabai, Quinn Jacobson
    Architectural Support for Software Transactional Memory. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:185-196 [Conf]
  8. Ali-Reza Adl-Tabatabai, Thomas R. Gross, Guei-Yuan Lueh
    Code Reuse in an Optimizing Compiler. [Citation Graph (0, 0)][DBLP]
    OOPSLA, 1996, pp:51-68 [Conf]
  9. Ali-Reza Adl-Tabatabai, Michal Cierniak, Guei-Yuan Lueh, Vishesh M. Parikh, James M. Stichnoth
    Fast, Effective Code Generation in a Just-In-Time Java Compiler. [Citation Graph (0, 0)][DBLP]
    PLDI, 1998, pp:280-290 [Conf]
  10. Ali-Reza Adl-Tabatabai, Thomas R. Gross
    Detection and Recovery of Endangered Variables Caused by Instruction Scheduling. [Citation Graph (0, 0)][DBLP]
    PLDI, 1993, pp:13-25 [Conf]
  11. Ali-Reza Adl-Tabatabai, Thomas R. Gross
    Source-Level Debugging of Scalar Optimized Code. [Citation Graph (0, 0)][DBLP]
    PLDI, 1996, pp:33-43 [Conf]
  12. Ali-Reza Adl-Tabatabai, Richard L. Hudson, Mauricio J. Serrano, Sreenivas Subramoney
    Prefetch inection based on hardware monitoring and object metadata. [Citation Graph (0, 0)][DBLP]
    PLDI, 2004, pp:267-276 [Conf]
  13. Ali-Reza Adl-Tabatabai, Geoff Langdale, Steven Lucco, Robert Wahbe
    Efficient and Language-Independent Mobile Programs. [Citation Graph (0, 0)][DBLP]
    PLDI, 1996, pp:127-136 [Conf]
  14. Ali-Reza Adl-Tabatabai, Brian T. Lewis, Vijay Menon, Brian R. Murphy, Bratin Saha, Tatiana Shpeisman
    Compiler and runtime support for efficient software transactional memory. [Citation Graph (0, 0)][DBLP]
    PLDI, 2006, pp:26-37 [Conf]
  15. Ali-Reza Adl-Tabatabai, Thomas R. Gross
    Evicted Variables and the Interaction of Global Register Allocation and Symbolic Debugging. [Citation Graph (0, 0)][DBLP]
    POPL, 1993, pp:371-383 [Conf]
  16. Vijay Menon, Neal Glew, Brian R. Murphy, Andrew McCreight, Tatiana Shpeisman, Ali-Reza Adl-Tabatabai, Leaf Petersen
    A verifiable SSA program representation for aggressive compiler optimization. [Citation Graph (0, 0)][DBLP]
    POPL, 2006, pp:397-408 [Conf]
  17. Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hudson, Chi Cao Minh, Ben Hertzberg
    McRT-STM: a high performance software transactional memory system for a multi-core runtime. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2006, pp:187-197 [Conf]
  18. Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha
    Transactional programming in a multi-core environment. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2007, pp:272- [Conf]
  19. Yang Ni, Vijay Menon, Ali-Reza Adl-Tabatabai, Antony L. Hosking, Richard L. Hudson, J. Eliot B. Moss, Bratin Saha, Tatiana Shpeisman
    Open nesting in software transactional memory. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2007, pp:68-78 [Conf]
  20. Ali-Reza Adl-Tabatabai, David Dice, Maurice Herlihy, Nir Shavit, Christos Kozyrakis, Christoph von Praun, Michael Scott
    Potential show-stoppers for transactional synchronization. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2007, pp:55- [Conf]
  21. Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha
    Unlocking concurrency. [Citation Graph (0, 0)][DBLP]
    ACM Queue, 2006, v:4, n:10, pp:24-33 [Journal]
  22. Guei-Yuan Lueh, Thomas R. Gross, Ali-Reza Adl-Tabatabai
    Fusion-based register allocation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2000, v:22, n:3, pp:431-470 [Journal]
  23. Ali-Reza Adl-Tabatabai, Anwar M. Ghuloum, Shobhit O. Kanaujia
    Compression in cache design. [Citation Graph (0, 0)][DBLP]
    ICS, 2007, pp:190-201 [Conf]
  24. Tatiana Shpeisman, Vijay Menon, Ali-Reza Adl-Tabatabai, Steven Balensiefer, Dan Grossman, Richard L. Hudson, Katherine F. Moore, Bratin Saha
    Enforcing isolation and ordering in STM. [Citation Graph (0, 0)][DBLP]
    PLDI, 2007, pp:78-88 [Conf]
  25. Bratin Saha, Ali-Reza Adl-Tabatabai, Anwar M. Ghuloum, Mohan Rajagopalan, Richard L. Hudson, Leaf Petersen, Vijay Menon, Brian R. Murphy, Tatiana Shpeisman, Eric Sprangle, Anwar Rohillah, Doug Carmean, Jesse Fang
    Enabling scalability and performance in a large scale CMP environment. [Citation Graph (0, 0)][DBLP]
    EuroSys, 2007, pp:73-86 [Conf]

  26. Fault-safe code motion for type-safe languages. [Citation Graph (, )][DBLP]

  27. A Uniform Transactional Execution Environment for Java. [Citation Graph (, )][DBLP]

  28. NePaLTM: Design and Implementation of Nested Parallelism for Transactional Memory Systems. [Citation Graph (, )][DBLP]

  29. An analytic model of optimistic Software Transactional Memory. [Citation Graph (, )][DBLP]

  30. Architecting a chunk-based memory race recorder in modern CMPs. [Citation Graph (, )][DBLP]

  31. Design and implementation of transactional constructs for C/C++. [Citation Graph (, )][DBLP]

  32. Dynamic optimization for efficient strong atomicity. [Citation Graph (, )][DBLP]

  33. Concurrent GC leveraging transactional memory. [Citation Graph (, )][DBLP]

  34. NePalTM: design and implementation of nested parallelism for transactional memory systems. [Citation Graph (, )][DBLP]

  35. Practical weak-atomicity semantics for java stm. [Citation Graph (, )][DBLP]

  36. Kicking the tires of software transactional memory: why the going gets tough. [Citation Graph (, )][DBLP]

  37. Irrevocable transactions and their applications. [Citation Graph (, )][DBLP]

  38. Optimizing transactions for captured memory. [Citation Graph (, )][DBLP]

  39. Towards transactional memory semantics for C++. [Citation Graph (, )][DBLP]

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