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Ramaswamy Govindarajan:
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Publications of Author
- Kaushik Rajan, R. Govindarajan
Two-level mapping based cache index selection for packet forwarding engines. [Citation Graph (0, 0)][DBLP] PACT, 2006, pp:212-221 [Conf]
- Rad Silvera, Jian Wang, Ramaswamy Govindarajan, Guang R. Gao
A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors. [Citation Graph (0, 0)][DBLP] IEEE PACT, 1997, pp:78-89 [Conf]
- Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors. [Citation Graph (0, 0)][DBLP] ASAP, 2000, pp:329-338 [Conf]
- Chihong Zhang, Ramaswamy Govindarajan, Sean Ryan, Guang R. Gao
Efficient State-Diagram Construction Methods for Software Pipelining. [Citation Graph (0, 0)][DBLP] CC, 1999, pp:153-167 [Conf]
- Hongbo Rong, Alban Douillet, Ramaswamy Govindarajan, Guang R. Gao
Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops. [Citation Graph (0, 0)][DBLP] CGO, 2004, pp:175-188 [Conf]
- Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao
Single-Dimension Software Pipelining for Multi-Dimensional Loops. [Citation Graph (0, 0)][DBLP] CGO, 2004, pp:163-174 [Conf]
- Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao
A Framework for Resource-Constrained Rate-Optimal Software Pipelining. [Citation Graph (0, 0)][DBLP] CONPAR, 1994, pp:640-651 [Conf]
- Ramaswamy Govindarajan, Shashank S. Nemawarkar
A Large Context Multithreaded Architecture. [Citation Graph (0, 0)][DBLP] CONPAR, 1992, pp:423-428 [Conf]
- V. Janaki Ramanan, Ramaswamy Govindarajan
Resource Usage Modelling for Software Pipelining. [Citation Graph (0, 0)][DBLP] HiPC, 1999, pp:111-119 [Conf]
- Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao
Co-Scheduling Hardware and Software Pipelines. [Citation Graph (0, 0)][DBLP] HPCA, 1996, pp:52-61 [Conf]
- Ramaswamy Govindarajan, Shashank S. Nemawarkar, Phillip LeNir
Design and Performance Evaluation of a Multithreaded Architecture. [Citation Graph (0, 0)][DBLP] HPCA, 1995, pp:298-307 [Conf]
- Hongbo Yang, Ramaswamy Govindarajan, Guang R. Gao, Kevin B. Theobald
Power-Performance Trade-Offs for Energy-Efficient Architectures: A Quantitative Study. [Citation Graph (0, 0)][DBLP] ICCD, 2002, pp:174-179 [Conf]
- Shashank S. Nemawarkar, Ramaswamy Govindarajan, Guang R. Gao, Vinod K. Agarwal
Performance Evaluation of Latency Tolerant Architectures. [Citation Graph (0, 0)][DBLP] ICCI, 1992, pp:183-186 [Conf]
- Kaushik Rajan, R. Govindarajan
A heterogeneously segmented cache architecture for a packet forwarding engine. [Citation Graph (0, 0)][DBLP] ICS, 2005, pp:71-80 [Conf]
- V. Janaki Ramanan, Ramaswamy Govindarajan
Resource usage models for instruction scheduling: two new models and a classification. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1999, pp:417-424 [Conf]
- Amod K. Dani, V. Janaki Ramanan, Ramaswamy Govindarajan
Register-Sensitive Software Pipelining. [Citation Graph (0, 0)][DBLP] IPPS/SPDP, 1998, pp:194-198 [Conf]
- Guang R. Gao, Kevin B. Theobald, Ramaswamy Govindarajan, Clement Leung, Ziang Hu, Haiping Wu, Jizhu Lu, Juan del Cuvillo, Adeline Jacquet, Vincent Janot, Thomas L. Sterling
Programming Models and System Software for Future High-End Computing Systems: Work-in-Progress. [Citation Graph (0, 0)][DBLP] IPDPS, 2003, pp:206- [Conf]
- Ramaswamy Govindarajan, N. S. S. Narasimha Rao, Erik R. Altman, Guang R. Gao
An Enhanced Co-Scheduling Method Using Reduced MS-State Diagrams. [Citation Graph (0, 0)][DBLP] IPPS/SPDP, 1998, pp:168-175 [Conf]
- Ramaswamy Govindarajan, Hongbo Yang, Chihong Zhang, José Nelson Amaral, Guang R. Gao
Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs. [Citation Graph (0, 0)][DBLP] IPDPS, 2001, pp:26- [Conf]
- Adeline Jacquet, Vincent Janot, Clement Leung, Guang R. Gao, Ramaswamy Govindarajan, Thomas L. Sterling
An Executable Analytical Performance Evaluation Approach for Early Performance Prediction. [Citation Graph (0, 0)][DBLP] IPDPS, 2003, pp:268- [Conf]
- Erik R. Altman, Guang R. Gao, Ramaswamy Govindarajan
An Experimental Study of an ILP-based Exact Solution Method for Software Pipelining. [Citation Graph (0, 0)][DBLP] LCPC, 1995, pp:16-30 [Conf]
- Ramaswamy Govindarajan, Chihong Zhang, Guang R. Gao
Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors. [Citation Graph (0, 0)][DBLP] LCPC, 1999, pp:70-84 [Conf]
- Hongbo Yang, Ramaswamy Govindarajan, Guang R. Gao, Ziang Hu
Compiler-Assisted Cache Replacement: Problem Formulation and Performance Evaluation. [Citation Graph (0, 0)][DBLP] LCPC, 2003, pp:77-92 [Conf]
- Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao
Minimizing register requirements under resource-constrained rate-optimal software pipelining. [Citation Graph (0, 0)][DBLP] MICRO, 1994, pp:85-94 [Conf]
- Philip Lenir, Ramaswamy Govindarajan, Shashank S. Nemawarkar
Exploiting instruction-level parallelism: the multithreaded approach. [Citation Graph (0, 0)][DBLP] MICRO, 1992, pp:189-192 [Conf]
- Shashank S. Nemawarkar, Ramaswamy Govindarajan, Guang R. Gao, Vinod K. Agarwal
Performance of Interconnection Network in Multithreaded Architectures. [Citation Graph (0, 0)][DBLP] PARLE, 1994, pp:823-826 [Conf]
- Erik R. Altman, Ramaswamy Govindarajan, Guang R. Gao
Scheduling and Mapping: Software Pipelining in the Presence of Structural Hazards. [Citation Graph (0, 0)][DBLP] PLDI, 1995, pp:139-150 [Conf]
- Ramaswamy Govindarajan, Shashank S. Nemawarkar
SMALL: A Scalable Multithreaded Architecture to Exploit Large Localiy. [Citation Graph (0, 0)][DBLP] SPDP, 1992, pp:32-39 [Conf]
- Shashank S. Nemawarkar, Ramaswamy Govindarajan, Guang R. Gao, Vinod K. Agarwal
Analysis of Multithreaded Multiprocessors with Distributed Shared Memory. [Citation Graph (0, 0)][DBLP] SPDP, 1993, pp:114-121 [Conf]
- Ramaswamy Govindarajan, N. S. S. Narasimha Rao, Erik R. Altman, Guang R. Gao
Enhanced Co-Scheduling: A Software Pipelining Method Using Modulo-Scheduled Pipeline Theory. [Citation Graph (0, 0)][DBLP] International Journal of Parallel Programming, 2000, v:28, n:1, pp:1-46 [Journal]
- Erik R. Altman, Ramaswamy Govindarajan, Guang R. Gao
A Unified Framework for Instruction Scheduling and Mapping for Function Units with Structural Hazards. [Citation Graph (0, 0)][DBLP] J. Parallel Distrib. Comput., 1998, v:49, n:2, pp:259-293 [Journal]
- Ramaswamy Govindarajan, Anand Sivasubramaniam
Guest Editors' Introduction: Special Issue on Cluster and Network-Based Computing. [Citation Graph (0, 0)][DBLP] J. Parallel Distrib. Comput., 2001, v:61, n:11, pp:1507-1511 [Journal]
- Ramaswamy Govindarajan, Hongbo Yang, José Nelson Amaral, Chihong Zhang, Guang R. Gao
Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2003, v:52, n:1, pp:4-20 [Journal]
- Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao
A Framework for Resource-Constrained Rate-Optimal Software Pipelining. [Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 1996, v:7, n:11, pp:1133-1149 [Journal]
- Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao
Single-dimension software pipelining for multidimensional loops. [Citation Graph (0, 0)][DBLP] TACO, 2007, v:4, n:1, pp:- [Journal]
Region Based Structure Layout Optimization by Selective Data Copying. [Citation Graph (, )][DBLP]
Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses. [Citation Graph (, )][DBLP]
Scalable Context-Sensitive Points-to Analysis Using Multi-dimensional Bloom Filters. [Citation Graph (, )][DBLP]
Emulating Optimal Replacement with a Shepherd Cache. [Citation Graph (, )][DBLP]
Points-to Analysis as a System of Linear Equations. [Citation Graph (, )][DBLP]
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