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Mikhail Smelyanskiy:
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- Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson
Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. [Citation Graph (0, 0)][DBLP] IEEE PACT, 2000, pp:3-12 [Conf]
- Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke
Systematic Register Bypass Customization for Application-Specific Processors. [Citation Graph (0, 0)][DBLP] ASAP, 2003, pp:64-74 [Conf]
- Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson
Probabilistic Predicate-Aware Modulo Scheduling. [Citation Graph (0, 0)][DBLP] CGO, 2004, pp:151-162 [Conf]
- Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson, Hsien-Hsin S. Lee
Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints. [Citation Graph (0, 0)][DBLP] CGO, 2003, pp:169-178 [Conf]
- Hsien-Hsin S. Lee, Mikhail Smelyanskiy, Chris J. Newburn, Gary S. Tyson
Stack Value File: Custom Microarchitecture for the Stack. [Citation Graph (0, 0)][DBLP] HPCA, 2001, pp:5-14 [Conf]
Atomic Vector Operations on Chip Multiprocessors. [Citation Graph (, )][DBLP]
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU. [Citation Graph (, )][DBLP]
Scaling performance of interior-point method on large-scale chip multiprocessor system. [Citation Graph (, )][DBLP]
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