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Gary S. Tyson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson
    Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:3-12 [Conf]
  2. Hsien-Hsin S. Lee, Gary S. Tyson
    Region-based caching: an energy-delay efficient memory architecture for embedded processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:120-127 [Conf]
  3. Stephen Hines, David B. Whalley, Gary S. Tyson
    Adapting compilation techniques to enhance the packing of instructions into registers. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:43-53 [Conf]
  4. Michael J. Geiger, Sally A. McKee, Gary S. Tyson
    Drowsy region-based caches: minimizing both dynamic and static power dissipation. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:378-384 [Conf]
  5. Prasad Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson
    Exhaustive Optimization Phase Order Space Exploration. [Citation Graph (0, 0)][DBLP]
    CGO, 2006, pp:306-318 [Conf]
  6. Prasad Kulkarni, David B. Whalley, Gary S. Tyson
    Evaluating Heuristic Optimization Phase Order Search Algorithms. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:157-169 [Conf]
  7. Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge
    FITS: framework-based instruction-set tuning synthesis for embedded application specific processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:920-923 [Conf]
  8. Michael J. Geiger, Sally A. McKee, Gary S. Tyson
    Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:102-115 [Conf]
  9. Hsien-Hsin S. Lee, Mikhail Smelyanskiy, Chris J. Newburn, Gary S. Tyson
    Stack Value File: Custom Microarchitecture for the Stack. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:5-14 [Conf]
  10. Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak
    Branch History Guided Instruction Prefetching. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:291-300 [Conf]
  11. Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson
    Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:133-141 [Conf]
  12. Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary S. Tyson, Todd M. Austin
    Classifying load and store instructions for memory renaming. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:399-407 [Conf]
  13. Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens
    Utilizing Reuse Information in Data Cache Management. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:449-456 [Conf]
  14. Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun
    A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:338-347 [Conf]
  15. Stephen Hines, Joshua Green, Gary S. Tyson, David B. Whalley
    Improving Program Efficiency by Packing Instructions into Registers. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:260-271 [Conf]
  16. William C. Kreahling, Stephen Hines, David B. Whalley, Gary S. Tyson
    Reducing the cost of conditional transfers of control by using comparison specifications. [Citation Graph (0, 0)][DBLP]
    LCTES, 2006, pp:64-71 [Conf]
  17. Prasad Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson
    In search of near-optimal optimization phase orderings. [Citation Graph (0, 0)][DBLP]
    LCTES, 2006, pp:83-92 [Conf]
  18. Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson
    mlcache: A Flexible Multi-Lateral Cache Simulator. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 1998, pp:19-26 [Conf]
  19. Matthew K. Farrens, Arvin Park, Gary S. Tyson
    Modifying VM hardware to reduce address pin requirements. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:210-213 [Conf]
  20. Stephen Hines, Gary S. Tyson, David B. Whalley
    Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:19-29 [Conf]
  21. Sangwook P. Kim, Gary S. Tyson
    Analyzing the Working Set Characteristics of Branch Execution. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:49-58 [Conf]
  22. Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens
    Eager writeback - a technique for improving bandwidth utilization. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:11-21 [Conf]
  23. Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin
    On High-Bandwidth Data Cache Design for Multi-Issue Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:46-56 [Conf]
  24. Gary S. Tyson
    The effects of predicated execution on branch prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:196-206 [Conf]
  25. Gary S. Tyson, Todd M. Austin
    Improving the Accuracy and Performance of Memory Communication Through Renaming. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:218-227 [Conf]
  26. Gary S. Tyson, Matthew K. Farrens
    Techniques for extracting instruction level parallelism on MIMD architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:128-137 [Conf]
  27. Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun
    A modified approach to data cache management. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:93-103 [Conf]
  28. Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun
    MISC: a Multiple Instruction Stream Computer. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:193-196 [Conf]
  29. Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson
    Improving BTB performance in the presence of DLLs. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:77-86 [Conf]
  30. Allen C. Cheng, Gary S. Tyson
    High-quality ISA synthesis for low-power cache designs in embedded microprocessors. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2006, v:50, n:2-3, pp:299-310 [Journal]
  31. Gary S. Tyson, Todd M. Austin
    Memory Renaming: Fast, Early and Accurate Processing of Memory Communication. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:5, pp:357-380 [Journal]
  32. Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens
    Improving Bandwidth Utilization using Eager Writeback. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2001, v:3, n:, pp:- [Journal]
  33. Matt Postiff, Gary S. Tyson, Trevor N. Mudge
    Performance Limits of Trace Caches. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 1999, v:1, n:, pp:- [Journal]
  34. Allen C. Cheng, Gary S. Tyson
    An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:6, pp:698-713 [Journal]
  35. Viji Srinivasan, Edward S. Davidson, Gary S. Tyson
    A Prefetch Taxonomy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:2, pp:126-140 [Journal]
  36. Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson
    Active Management of Data Caches by Exploiting Reuse Information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:11, pp:1244-1259 [Journal]
  37. Chris Zimmer, Stephen Roderick Hines, Prasad Kulkarni, Gary S. Tyson, David B. Whalley
    Facilitating compiler optimizations through the dynamic mapping of alternate register structures. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:165-169 [Conf]
  38. Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson
    Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:23-37 [Conf]
  39. Stephen Roderick Hines, Gary S. Tyson, David B. Whalley
    Addressing instruction fetch bottlenecks by using an instruction register file. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:165-174 [Conf]

  40. Core monitors: monitoring performance in multicore processors. [Citation Graph (, )][DBLP]


  41. Enhancing the effectiveness of utilizing an instruction register file. [Citation Graph (, )][DBLP]


  42. PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis. [Citation Graph (, )][DBLP]


  43. Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE). [Citation Graph (, )][DBLP]


  44. Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache. [Citation Graph (, )][DBLP]


  45. Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education. [Citation Graph (, )][DBLP]


  46. Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education [Citation Graph (, )][DBLP]


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