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Title:
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Josep Llosa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Xavier Vera, Jaume Abella, Antonio González, Josep Llosa
    Optimizing Program Locality Through CMEs and GAs. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2003, pp:68-78 [Conf]
  2. Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé
    Using Sacks to Organize Registers in VLIW Machines. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1994, pp:628-639 [Conf]
  3. Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham
    Allocating Lifetimes to Queues in Software Pipelined Architectures. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1997, pp:1066-1073 [Conf]
  4. Xavier Vera, Josep Llosa, Antonio González, Nerina Bermudo
    A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:194-198 [Conf]
  5. Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham
    Distributed Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:130-134 [Conf]
  6. Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
    Out-of-Order Commit Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:48-59 [Conf]
  7. Josep Llosa, Mateo Valero, Eduard Ayguadé
    Non-Consistent Dual Register Files to Reduce Register Pressure. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:22-31 [Conf]
  8. David López, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP, 1999, pp:22-29 [Conf]
  9. Jaume Abella, Antonio González, Josep Llosa, Xavier Vera
    Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2002, pp:568-580 [Conf]
  10. Josep M. Codina, Josep Llosa, Antonio González
    A comparative study of modulo scheduling techniques. [Citation Graph (0, 0)][DBLP]
    ICS, 2002, pp:97-106 [Conf]
  11. David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
    Resource Widening Versus Replication: Limits and Performance-cost Trade-off. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:441-448 [Conf]
  12. David López, Mateo Valero, Josep Llosa, Eduard Ayguadé
    Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:12-19 [Conf]
  13. Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham
    Partitioned Schedules for Clustered VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:386-391 [Conf]
  14. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Hierarchical Clustered Register File Organization for VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:77- [Conf]
  15. Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
    Kilo-instruction Processors. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:10-25 [Conf]
  16. Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
    Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:113-126 [Conf]
  17. Xavier Vera, Josep Llosa, Antonio González
    Near-Optimal Padding for Removing Conflict Misses. [Citation Graph (0, 0)][DBLP]
    LCPC, 2002, pp:329-343 [Conf]
  18. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    MIRS: Modulo Scheduling with Integrated Register Spilling. [Citation Graph (0, 0)][DBLP]
    LCPC, 2001, pp:239-253 [Conf]
  19. Josep Llosa, Stefan M. Freudenberger
    Reduced code size modulo scheduling in the absence of hardware support. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:99-110 [Conf]
  20. Josep Llosa, Mateo Valero, Eduard Ayguadé
    Heuristics for Register-Constrained Software Pipelining. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:250-261 [Conf]
  21. Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
    Hypernode reduction modulo scheduling. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:350-360 [Conf]
  22. David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
    Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:237-246 [Conf]
  23. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Two-level hierarchical register file organization for VLIW processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:137-146 [Conf]
  24. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Modulo scheduling with integrated register spilling for clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:160-169 [Conf]
  25. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Improved spill code generation for software pipelined loops. [Citation Graph (0, 0)][DBLP]
    PLDI, 2000, pp:134-144 [Conf]
  26. Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
    with Wide Functional Units. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:88-97 [Conf]
  27. Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero
    A Case for Resource-conscious Out-of-order Processors. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2003, v:2, n:, pp:- [Journal]
  28. Josep Llosa, Eduard Ayguadé, Mateo Valero
    Quantitative Evaluation of Register Pressure on Software Pipelined Loops. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:2, pp:121-142 [Journal]
  29. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2004, v:32, n:6, pp:447-474 [Journal]
  30. Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero
    A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:3-10 [Journal]
  31. Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt
    Lifetime-Sensitive Modulo Scheduling in a Production Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:3, pp:234-249 [Journal]
  32. Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
    Modulo Scheduling with Reduced Register Pressure. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:6, pp:625-638 [Journal]
  33. David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
    Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:10, pp:1033-1051 [Journal]
  34. Xavier Vera, Jaume Abella, Josep Llosa, Antonio González
    An accurate cost model for guiding data locality transformations. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2005, v:27, n:5, pp:946-987 [Journal]
  35. Xavier Vera, Nerina Bermudo, Josep Llosa, Antonio González
    A fast and accurate framework to analyze and optimize cache memory behavior. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2004, v:26, n:2, pp:263-300 [Journal]
  36. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Register Constrained Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:5, pp:417-430 [Journal]

  37. Hybrid multithreading for VLIW processors. [Citation Graph (, )][DBLP]


  38. Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration. [Citation Graph (, )][DBLP]


  39. Merge Logic for Clustered Multithreaded VLIW Processors. [Citation Graph (, )][DBLP]


  40. Cluster-level simultaneous multithreading for VLIW processors. [Citation Graph (, )][DBLP]


  41. Thread Merging Schemes for Multithreaded Clustered VLIW Processors. [Citation Graph (, )][DBLP]


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