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Sanjay J. Patel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nicholas J. Wang, Michael Fertig, Sanjay J. Patel
    Y-Branches: When You Come to a Fork in the Road, Take It. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2003, pp:56-0 [Conf]
  2. Francesco Spadini, Brian Fahs, Sanjay J. Patel, Steven S. Lumetta
    Improving Quasi-Dynamic Schedules through Region Slip. [Citation Graph (0, 0)][DBLP]
    CGO, 2003, pp:149-158 [Conf]
  3. Dina L. McKinney, Daniel L. Leibholz, Mark B. Rosenbluth, James R. Mullens, Kwong-Tak A. Chui, Masooma Bhaiwala, Sanjay J. Patel, Christopher L. Houghton, Delvan A. Ramey
    DECchip 21066: The Alpha AXP Chip for Cost-Focused Systems. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1994, pp:406-413 [Conf]
  4. Sanjay J. Patel, Janak H. Patel
    Effectiveness of heuristics measures for automatic test pattern generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:547-552 [Conf]
  5. Nicholas J. Wang, Sanjay J. Patel
    ReStore: Symptom Based Soft Error Detection in Microprocessors. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:30-39 [Conf]
  6. Nicholas J. Wang, Justin Quek, Todd M. Rafacz, Sanjay J. Patel
    Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline. [Citation Graph (0, 0)][DBLP]
    DSN, 2004, pp:61-0 [Conf]
  7. Todd E. Ehrhart, Sanjay J. Patel
    Reducing the Scheduling Critical Cycle Using Wakeup Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:222-231 [Conf]
  8. Wen-mei W. Hwu, Sanjay J. Patel
    The Future of Computer Architecture Research: An Industrial Perspective. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:264- [Conf]
  9. Brian Slechta, David Crowe, Brian Fahs, Michael Fertig, Gregory A. Muthler, Justin Quek, Francesco Spadini, Sanjay J. Patel, Steven Lumetta
    Dynamic Optimization of Micro-Operations. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:165-0 [Conf]
  10. Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt
    An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:52-61 [Conf]
  11. Brian Fahs, Todd M. Rafacz, Sanjay J. Patel, Steven S. Lumetta
    Continuous Optimization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:86-97 [Conf]
  12. Sanjay J. Patel, Marius Evers, Yale N. Patt
    Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:262-271 [Conf]
  13. Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu
    Beating in-order stalls with "flea-flicker" two-pass pipelining. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:387-398 [Conf]
  14. Brian Fahs, Satarupa Bose, Matthew M. Crum, Brian Slechta, Francesco Spadini, Tony Tung, Sanjay J. Patel, Steven S. Lumetta
    Performance characterization of a hardware mechanism for dynamic optimization. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:16-27 [Conf]
  15. Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
    Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:24-33 [Conf]
  16. Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
    Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:173-181 [Conf]
  17. Gregory A. Muthler, David Crowe, Sanjay J. Patel, Steven Lumetta
    Instruction fetch deferral using static slack. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:51-61 [Conf]
  18. Sanjay J. Patel, Tony Tung, Satarupa Bose, Matthew M. Crum
    Increasing the size of atomic instruction blocks using control flow assertions. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:303-313 [Conf]
  19. Steven Lumetta, Sanjay J. Patel
    Characterization of essential dynamic instructions. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2003, pp:308-309 [Conf]
  20. Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark
    One Billion Transistors, One Uniprocessor, One Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:9, pp:51-57 [Journal]
  21. Dina L. McKinney, Masooma Bhaiwala, Kwong-Tak A. Chui, Christopher L. Houghton, James R. Mullens, Daniel L. Leibholz, Sanjay J. Patel, Delvan A. Ramey, Mark B. Rosenbluth
    Digital;s DECchip 21066: The First Cost-focused Alpha AXP Chip [Citation Graph (0, 0)][DBLP]
    Digital Technical Journal, 1994, v:6, n:1, pp:0-0 [Journal]
  22. Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer
    An Experimental Study of Soft Errors in Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:6, pp:30-39 [Journal]
  23. Ronald D. Barnes, John W. Sias, Erik M. Nystrom, Sanjay J. Patel, Jose (Nacho) Navarro, Wen-mei W. Hwu
    Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:1, pp:18-33 [Journal]
  24. Sanjay J. Patel, Daniel H. Friendly, Yale N. Patt
    Evaluation of Design Options for the Trace Cache Fetch Mechanism. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:193-204 [Journal]
  25. Sanjay J. Patel, Steven Lumetta
    rePLay: A Hardware Framework for Dynamic Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:6, pp:590-608 [Journal]
  26. Nicholas J. Wang, Sanjay J. Patel
    ReStore: Symptom-Based Soft Error Detection in Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Dependable Sec. Comput., 2006, v:3, n:3, pp:188-201 [Journal]
  27. Wen-mei W. Hwu, Shane Ryoo, Sain-zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel Mahesri, Stephanie C. Tsao, Nacho Navarro, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel
    Implicitly Parallel Programming Models for Thousand-Core Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:754-759 [Conf]
  28. Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel
    Examining ACE analysis reliability estimates using fault-injection. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:460-469 [Conf]
  29. Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman
    ParallAX: an architecture for real-time physics. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:232-243 [Conf]

  30. A Task-Centric Memory Model for Scalable Accelerator Architectures. [Citation Graph (, )][DBLP]

  31. Optimization of tele-immersion codes. [Citation Graph (, )][DBLP]

  32. An asymmetric distributed shared memory model for heterogeneous parallel systems. [Citation Graph (, )][DBLP]

  33. GoldMine: Automatic assertion generation using data mining and static analysis. [Citation Graph (, )][DBLP]

  34. An integrated framework for joint design space exploration of microarchitecture and circuits. [Citation Graph (, )][DBLP]

  35. Depth image-based rendering with low resolution depth. [Citation Graph (, )][DBLP]

  36. Rigel: an architecture and scalable programming interface for a 1000-core accelerator. [Citation Graph (, )][DBLP]

  37. Cohesion: a hybrid memory model for accelerators. [Citation Graph (, )][DBLP]

  38. Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. [Citation Graph (, )][DBLP]

  39. The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. [Citation Graph (, )][DBLP]

  40. Tradeoffs in designing accelerator architectures for visual computing. [Citation Graph (, )][DBLP]

  41. An adaptive performance modeling tool for GPU architectures. [Citation Graph (, )][DBLP]

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