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Zonghua Gu :
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Zonghua Gu , Zhimin He Real-Time Scheduling Techniques for Implementation Synthesis from Component-Based Software Models. [Citation Graph (0, 0)][DBLP ] CBSE, 2005, pp:235-250 [Conf ] Zonghua Gu , Kang G. Shin Integrated Modeling and Analysis of Computer-Based Embedded Control Systems. [Citation Graph (0, 0)][DBLP ] ECBS, 2003, pp:141-148 [Conf ] Zonghua Gu Timing Analysis of Distributed End-to-End Task Graphs with Model-Checking. [Citation Graph (0, 0)][DBLP ] EUC, 2005, pp:214-223 [Conf ] Zonghua Gu , Shige Wang , Sharath Kodase , Kang G. Shin Multi-View Modeling and Analysis of Embedded Real-Time Software with Meta-Modeling and Model Transformation. [Citation Graph (0, 0)][DBLP ] HASE, 2004, pp:32-41 [Conf ] Zonghua Gu , Kang G. Shin An Integrated Approach to Modeling and Analysis of Embedded Real-Time Systems Based on Timed Petri Net. [Citation Graph (0, 0)][DBLP ] ICDCS, 2003, pp:350-359 [Conf ] Zonghua Gu Solving Real-Time Scheduling Problems with Model-Checking. [Citation Graph (0, 0)][DBLP ] ICESS, 2005, pp:186-197 [Conf ] Zonghua Gu , Kang G. Shin Analysis of Event-Driven Real-Time Systems with Time Petri Nets: A Translation-Based Approach. [Citation Graph (0, 0)][DBLP ] DIPES, 2002, pp:31-40 [Conf ] Zonghua Gu , Kang G. Shin Model-Checking of Component-Based Event-Driven Real-Time Embedded Software. [Citation Graph (0, 0)][DBLP ] ISORC, 2005, pp:410-417 [Conf ] Zonghua Gu , Sharath Kodase , Shige Wang , Kang G. Shin A Model-Based Approach to System-Level Dependency and Real-Time Analysis of Embedded Software. [Citation Graph (0, 0)][DBLP ] IEEE Real Time Technology and Applications Symposium, 2003, pp:78-0 [Conf ] Sharath Kodase , Shige Wang , Zonghua Gu , Kang G. Shin Improving Scalability of Task Allocation and Scheduling in Large Distributed Real-Time Systems Using Shared Buffers. [Citation Graph (0, 0)][DBLP ] IEEE Real Time Technology and Applications Symposium, 2003, pp:181-188 [Conf ] Zonghua Gu , Kang G. Shin Synthesis of Real-Time Implementations from Component-Based Software Models. [Citation Graph (0, 0)][DBLP ] RTSS, 2005, pp:167-176 [Conf ] Zonghua Gu , Shige Wang , Sharath Kodase , Kang G. Shin An End-to-End Tool Chain for Multi-View Modeling and Analysis of Avionics Mission Computing Software. [Citation Graph (0, 0)][DBLP ] RTSS, 2003, pp:78-0 [Conf ] Zonghua Gu , Xiuqiang He , Mingxuan Yuan Optimization of Static Task and Bus Access Schedules for Time-Triggered Distributed Embedded Systems with Model-Checking. [Citation Graph (0, 0)][DBLP ] DAC, 2007, pp:294-299 [Conf ] Jin Cui , Qingxu Deng , Xiuqiang He , Zonghua Gu An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:129-134 [Conf ] Nan Guan , Zonghua Gu , Qingxu Deng , Weichen Liu , Ge Yu Improved Schedulability Analysis of EDF Scheduling on Reconfigurable Hardware Devices. [Citation Graph (0, 0)][DBLP ] IPDPS, 2007, pp:1-8 [Conf ] Zonghua Gu , Qingxu Deng QoS-Optimized Integration of Embedded Software Components with Multiple Modes of Execution. [Citation Graph (0, 0)][DBLP ] SEKE, 2007, pp:320-325 [Conf ] Nan Guan , Zonghua Gu , Qingxu Deng , Shuaihong Gao , Ge Yu Exact Schedulability Analysis for Static-Priority Global Multiprocessor Scheduling Using Model-Checking. [Citation Graph (0, 0)][DBLP ] SEUS, 2007, pp:263-272 [Conf ] Improving scalability of model-checking for minimizing buffer requirements of synchronous dataflow graphs. [Citation Graph (, )][DBLP ] Online adaptive utilization control for real-time embedded multiprocessor systems. [Citation Graph (, )][DBLP ] An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking. [Citation Graph (, )][DBLP ] Performance Comparison of Techniques on Static Path Analysis of WCET. [Citation Graph (, )][DBLP ] Teaching embedded systems software: The HKUST experience. [Citation Graph (, )][DBLP ] An Efficient Algorithm for Online Soft Real-Time Task Placement on Reconfigurable Hardware Devices. [Citation Graph (, )][DBLP ] Schedulability Analysis of Global Fixed-Priority or EDF Multiprocessor Scheduling with Symbolic Model-Checking. [Citation Graph (, )][DBLP ] Real-Time Component Composition Using Hierarchical Timed Automata. [Citation Graph (, )][DBLP ] Hardware/Software Partitioning and Static Task Scheduling on Runtime Reconfigurable FPGAs using a SMT Solver. [Citation Graph (, )][DBLP ] Optimal Static Task Scheduling on Reconfigurable Hardware Devices Using Model-Checking. [Citation Graph (, )][DBLP ] Power-Aware CPU Utilization Control for Distributed Real-Time Systems. [Citation Graph (, )][DBLP ] Static Scheduling and Software Synthesis for Dataflow Graphs with Symbolic Model-Checking. [Citation Graph (, )][DBLP ] Efficient SAT-Based Mapping and Scheduling of Homogeneous Synchronous Dataflow Graphs for Throughput Optimization. [Citation Graph (, )][DBLP ] Optimal Sampling Rate Assignment with Dynamic Route Selection for Real-Time Wireless Sensor Networks. [Citation Graph (, )][DBLP ] New Schedulability Test Conditions for Non-preemptive Scheduling on Multiprocessor Platforms. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.304secs