The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Thomas F. Wenisch: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Thomas F. Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Chris Gniady, Anastassia Ailamaki, Babak Falsafi
    Store-Ordered Streaming of Shared Memory. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:75-86 [Conf]
  2. Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe
    Statistical sampling of microarchitecture simulation. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  3. Stephen Somogyi, Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos
    Spatial Memory Streaming. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:252-263 [Conf]
  4. Thomas F. Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Anastassia Ailamaki, Babak Falsafi
    Temporal Streaming of Shared Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:222-233 [Conf]
  5. Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe
    SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:84-95 [Conf]
  6. Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe
    TurboSMARTS: accurate microarchitecture simulation sampling in minutes. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2005, pp:408-409 [Conf]
  7. Stephen Somogyi, Thomas F. Wenisch, Nikolaos Hardavellas, Jangwoo Kim, Anastassia Ailamaki, Babak Falsafi
    Memory coherence activity prediction in commercial workloads. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:37-45 [Conf]
  8. Thomas F. Wenisch, Roland E. Wunderlich, Michael Ferdman, Anastassia Ailamaki, Babak Falsafi, James C. Hoe
    SimFlex: Statistical Sampling of Computer System Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:4, pp:18-31 [Journal]
  9. Nikolaos Hardavellas, Stephen Somogyi, Thomas F. Wenisch, Roland E. Wunderlich, Shelley Chen, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk
    SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS Performance Evaluation Review, 2004, v:31, n:4, pp:31-34 [Journal]
  10. Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe
    Statistical sampling of microarchitecture simulation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Model. Comput. Simul., 2006, v:16, n:3, pp:197-224 [Journal]
  11. Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos
    Mechanisms for store-wait-free multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:266-277 [Conf]

  12. PowerNap: eliminating server idle power. [Citation Graph (, )][DBLP]


  13. Power routing: dynamic power provisioning in the data center. [Citation Graph (, )][DBLP]


  14. Practical off-chip meta-data for temporal memory streaming. [Citation Graph (, )][DBLP]


  15. Disaggregated memory for expansion and sharing in blade servers. [Citation Graph (, )][DBLP]


  16. Spatio-temporal memory streaming. [Citation Graph (, )][DBLP]


  17. InvisiFence: performance-transparent memory ordering in conventional multiprocessors. [Citation Graph (, )][DBLP]


  18. Thinking outside the box: power management at the system level & beyond. [Citation Graph (, )][DBLP]


  19. Peak power modeling for data center servers with switched-mode power supplies. [Citation Graph (, )][DBLP]


  20. Simulation sampling with live-points. [Citation Graph (, )][DBLP]


  21. Temporal instruction fetch streaming. [Citation Graph (, )][DBLP]


  22. Temporal streams in commercial server applications. [Citation Graph (, )][DBLP]


Search in 0.133secs, Finished in 0.135secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002