The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Alex Orailoglu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chengmo Yang, Alex Orailoglu
    Power-efficient instruction delivery through trace reuse. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:192-201 [Conf]
  2. Raid Ayoub, Alex Orailoglu
    A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:729-734 [Conf]
  3. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Fault tolerant nanoelectronic processor architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:311-316 [Conf]
  4. Ozgur Sinanoglu, Alex Orailoglu
    Efficient RT-level fault diagnosis methodology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:212-217 [Conf]
  5. Rasit Onur Topaloglu, Alex Orailoglu
    On mismatch in the deep sub-micron era - from physics to circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:62-67 [Conf]
  6. Rasit Onur Topaloglu, Alex Orailoglu
    Forward discrete probability propagation method for device performance characterization under process variations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:220-223 [Conf]
  7. Tongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu
    Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1192-1195 [Conf]
  8. Sobeeh Almukhaizim, Peter Petrov, Alex Orailoglu
    Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:319-324 [Conf]
  9. Baris Arslan, Alex Orailoglu
    Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:230-235 [Conf]
  10. Ismet Bayraktaroglu, Alex Orailoglu
    Accumulation-based concurrent fault detection for linear digital state variable systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:484-0 [Conf]
  11. Ismet Bayraktaroglu, Alex Orailoglu
    Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck? [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:373-378 [Conf]
  12. Ismet Bayraktaroglu, K. Udawatta, Alex Orailoglu
    An Examination of PRPG Selection Approaches for Large, Industrial Designs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:440-0 [Conf]
  13. Yiorgos Makris, Jamison Collins, Alex Orailoglu
    Fast hierarchical test path construction for DFT-free controller-datapath circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:185-190 [Conf]
  14. Yiorgos Makris, Alex Orailoglu
    Test Requirement Analysis for Low Cost Hierarchical Test Path Construction. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:134-139 [Conf]
  15. Ozgur Sinanoglu, Alex Orailoglu
    Compaction Schemes with Minimum Test Application Time. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:199-204 [Conf]
  16. Ozgur Sinanoglu, Alex Orailoglu
    Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:202-209 [Conf]
  17. Chengmo Yang, Alex Orailoglu
    Power efficient branch prediction through early identification of branch addresses. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:169-178 [Conf]
  18. Peter Petrov, Alex Orailoglu
    Towards effective embedded processors in codesigns: customizable partitioned caches. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:79-84 [Conf]
  19. Peter Petrov, Alex Orailoglu
    Energy frugal tags in reprogrammable I-caches for application-specific embedded processors. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:181-186 [Conf]
  20. Ismet Bayraktaroglu, Alex Orailoglu
    Improved fault diagnosis in scan-based BIST via superposition. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:55-58 [Conf]
  21. Ismet Bayraktaroglu, Alex Orailoglu
    Test Volume and Application Time Reduction Through Scan Chain Concealment. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:151-155 [Conf]
  22. Laurence Goodby, Alex Orailoglu
    Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:813-818 [Conf]
  23. Laurence Goodby, Alex Orailoglu
    Frequency-Domain Compatibility in Digital Filter BIST. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:540-545 [Conf]
  24. Ian G. Harris, Alex Orailoglu
    Microarchitectural Synthesis of VLSI Designs with High Test Concurrency. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:206-211 [Conf]
  25. Ramesh Karri, Alex Orailoglu
    Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:662-665 [Conf]
  26. Ramesh Karri, Alex Orailoglu
    High-Level Synthesis of Fault-Secure Microarchitectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:429-433 [Conf]
  27. Ramesh Karri, Alex Orailoglu
    Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:552-556 [Conf]
  28. Alex Orailoglu, Daniel Gajski
    Flow graph representation. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:503-509 [Conf]
  29. Peter Petrov, Alex Orailoglu
    Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:512-517 [Conf]
  30. Peter Petrov, Daniel Tracy, Alex Orailoglu
    Energy-effcient physically tagged caches for embedded processors with virtual memory. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:17-22 [Conf]
  31. Wenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu
    Test application time and volume compression through seed overlapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:732-737 [Conf]
  32. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Topology aware mapping of logic functions onto nanowire-based crossbar architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:723-726 [Conf]
  33. Rasit Onur Topaloglu, Alex Orailoglu
    A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:851-856 [Conf]
  34. Baris Arslan, Alex Orailoglu
    CircularScan: A Scan Architecture for Test Cost Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1290-1295 [Conf]
  35. Ismet Bayraktaroglu, Alex Orailoglu
    Diagnosis for scan-based BIST: reaching deep into the signatures. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:102-111 [Conf]
  36. Ismet Bayraktaroglu, Alex Orailoglu
    Gate Level Fault Diagnosis in Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:376-381 [Conf]
  37. Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu
    Test Planning and Design Space Exploration in a Core-Based Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:478-485 [Conf]
  38. Laurence Goodby, Alex Orailoglu
    Test Quality and Fault Risk in Digital Filter Datapath BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:468-475 [Conf]
  39. Samuel Norman Hamilton, Alex Orailoglu
    Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:604-0 [Conf]
  40. Samuel Norman Hamilton, Alex Orailoglu, Andre Hertwig
    Self Recovering Controller and Datapath Codesign. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:596-601 [Conf]
  41. Yiorgos Makris, Alex Orailoglu
    Channel-Based Behavioral Test Synthesis for Improved Module Reachability. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:283-288 [Conf]
  42. Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu
    Test Synthesis for Mixed-Signal SOC Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:128-133 [Conf]
  43. Peter Petrov, Alex Orailoglu
    Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1065-1071 [Conf]
  44. Peter Petrov, Alex Orailoglu
    Power Efficiency through Application-Specific Instruction Memory Transformations. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10030-10035 [Conf]
  45. Wenjing Rao, Alex Orailoglu
    Virtual Compression through Test Vector Stitching for Scan Based Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10104-10109 [Conf]
  46. Sherief Reda, Alex Orailoglu
    Reducing Test Application Time Through Test Data Mutation Encoding. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:387-395 [Conf]
  47. Ozgur Sinanoglu, Alex Orailoglu
    Scan Power Minimization through Stimulus and Response Transformations. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:404-409 [Conf]
  48. Samuel Norman Hamilton, Alex Orailoglu
    Transient and Intermittent Fault Recovery without Rollback. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:252-260 [Conf]
  49. Yiorgos Makris, Alex Orailoglu
    A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:339-347 [Conf]
  50. Alex Orailoglu
    Graceful Degradation in Synthesis of VLSI ICs. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:301-311 [Conf]
  51. Sule Ozev, Alex Orailoglu
    Low-Cost Test for Large Analog IC's. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:101-0 [Conf]
  52. Ozgur Sinanoglu, Alex Orailoglu
    Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:325-333 [Conf]
  53. Peter Petrov, Alex Orailoglu
    Customizable Embedded Processor Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:468-475 [Conf]
  54. Peter Petrov, Alex Orailoglu
    Low-power Branch Target Buffer for Application-Specific Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:158-165 [Conf]
  55. Ozgur Sinanoglu, Alex Orailoglu
    Hierarchical Constraint Conscious RT-level Test Generation. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:312-318 [Conf]
  56. Ian G. Harris, Alex Orailoglu
    Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:119-123 [Conf]
  57. Samuel Norman Hamilton, Alex Orailoglu
    Microarchitectural Synthesis of ICs with Embedded Concurrent Fault Isolation. [Citation Graph (0, 0)][DBLP]
    FTCS, 1997, pp:329-338 [Conf]
  58. Ramesh Karri, Alex Orailoglu
    Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:519-526 [Conf]
  59. Ramesh Karri, Alex Orailoglu
    Optimal Self-Recovering Microarchitecture Synthesis. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:512-521 [Conf]
  60. Baris Arslan, Alex Orailoglu
    Design space exploration for aggressive test cost reduction in CircularScan architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:726-731 [Conf]
  61. Peter Petrov, Alex Orailoglu
    Compiler-Based Register Name Adjustment for Low-Power Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:523-528 [Conf]
  62. Wenjing Rao, Alex Orailoglu, G. Su
    Frugal linear network-based test decompression for drastic test cost reductions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:721-725 [Conf]
  63. Ozgur Sinanoglu, Alex Orailoglu
    A novel scan architecture for power-efficient, rapid test. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:299-303 [Conf]
  64. Ozgur Sinanoglu, Alex Orailoglu
    Partial Core Encryption for Performance-Efficient Test of SOCs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:91-94 [Conf]
  65. Baris Arslan, Alex Orailoglu
    Fault Dictionary Size Reduction through Test Response Superposition. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:480-0 [Conf]
  66. Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu
    Extending the Applicability of Parallel-Serial Scan Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:200-203 [Conf]
  67. Laurence Goodby, Alex Orailoglu, Paul M. Chau
    Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:323-326 [Conf]
  68. Ian G. Harris, Alex Orailoglu
    SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:101-104 [Conf]
  69. Karin Högstedt, Alex Orailoglu
    Integrating Binding Constraints in the Synthesis of Area-Efficient Self-Recovering Microarchitectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:331-334 [Conf]
  70. Alex Orailoglu
    Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:112-117 [Conf]
  71. Alex Orailoglu, Ian G. Harris
    Test Path Generation and Test Scheduling for Self-Testable Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:528-531 [Conf]
  72. Alex Orailoglu, Ramesh Karri
    High-Level Synthesis of Self-Recovering MicroArchitectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:286-289 [Conf]
  73. Sule Ozev, Alex Orailoglu
    Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:258-264 [Conf]
  74. Sule Ozev, Alex Orailoglu
    End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:72-77 [Conf]
  75. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:533-542 [Conf]
  76. Peter Petrov, Alex Orailoglu
    Virtual Page Tag Reduction for Low-power TLBs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:371-374 [Conf]
  77. Ozgur Sinanoglu, Alex Orailoglu
    Aggressive Test Power Reduction Through Test Stimuli Transformation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:542-547 [Conf]
  78. Ian G. Harris, Alex Orailoglu
    Intertwined Scheduling, Module Selection and Allocation in Time-and-Area. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1682-1685 [Conf]
  79. Sule Ozev, Alex Orailoglu, Hosam Haggag
    Automated test development and test time reduction for RF subsystems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:581-584 [Conf]
  80. Sule Ozev, Alex Orailoglu
    An Integrated Tool for Analog Test Generation and Fault Simulation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:267-272 [Conf]
  81. Sherief Reda, Rolf Drechsler, Alex Orailoglu
    On the Relation between SAT and BDDs for Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:394-399 [Conf]
  82. Alex Orailoglu, Peter Petrov
    Low-Power Data Memory Communication for Application-Specific Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:219-224 [Conf]
  83. Peter Petrov, Alex Orailoglu
    Data cache energy minimizations through programmable tag size matching to the applications. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:113-117 [Conf]
  84. Baris Arslan, Alex Orailoglu
    Test Cost Reduction Through A Reconfigurable Scan Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:945-952 [Conf]
  85. Ismet Bayraktaroglu, Alex Orailoglu
    Deterministic partitioning techniques for fault diagnosis in scan-based BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:273-282 [Conf]
  86. Laurence Goodby, Alex Orailoglu
    Towards 100% Testable FIR Digital Filters. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:394-402 [Conf]
  87. Yiorgos Makris, Alex Orailoglu
    DFT guidance through RTL test justification and propagation analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:668-0 [Conf]
  88. Christian Olgaard, Sule Ozev, Alex Orailoglu
    Testability implications in low-cost integrated radio transceivers: a Bluetooth case study. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:965-974 [Conf]
  89. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:472-478 [Conf]
  90. Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
    Scan Power Reduction Through Test Data Transition Frequency Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:844-850 [Conf]
  91. Ozgur Sinanoglu, Alex Orailoglu
    Space and time compaction schemes for embedded cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:521-529 [Conf]
  92. Ozgur Sinanoglu, Alex Orailoglu
    Modeling Scan Chain Modifications For Scan-in Test Power Minimization. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:602-611 [Conf]
  93. Ozgur Sinanoglu, Alex Orailoglu
    Autonomous Yet Deterministic Test of SOC Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1359-1368 [Conf]
  94. Ramesh Karri, Alex Orailoglu
    ALPS: An Algorithm for Pipeline Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:124-132 [Conf]
  95. Ismet Bayraktaroglu, Alex Orailoglu
    Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:113-120 [Conf]
  96. Ismet Bayraktaroglu, Alex Orailoglu
    Low-Cost On-Line Test for Digital Filters. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:446-451 [Conf]
  97. R. L. Campbell, P. Kuekes, David Y. Lepejian, W. Maly, Michael Nicolaidis, Alex Orailoglu
    Can Defect-Tolerant Chips Better Meet the Quality Challenge? [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:362-363 [Conf]
  98. Mingjing Chen, Hosam Haggag, Alex Orailoglu
    Decision Tree Based Mismatch Diagnosis in Analog Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:278-285 [Conf]
  99. Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu
    Invariance-Based On-Line Test for RTL Controller-Datapath Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:459-464 [Conf]
  100. Yiorgos Makris, Vishal Patel, Alex Orailoglu
    Efficient Transparency Extraction and Utilization in Hierarchical Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:246-251 [Conf]
  101. Sule Ozev, Alex Orailoglu
    Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:149-156 [Conf]
  102. Sule Ozev, Alex Orailoglu
    Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:213-222 [Conf]
  103. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:214-221 [Conf]
  104. Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
    Test Power Reduction through Minimization of Scan Chain Transitions. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:166-172 [Conf]
  105. Ozgur Sinanoglu, Alex Orailoglu
    RT-level Fault Simulation Based on Symbolic Propagation. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:240-245 [Conf]
  106. Mahsa Vahidi, Alex Orailoglu
    Testability metrics for synthesis of self-testable designs and effective test plans. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:170-175 [Conf]
  107. Ismet Bayraktaroglu, Alex Orailoglu
    Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:1, pp:42-53 [Journal]
  108. Ramesh Karri, Karin Högstedt, Alex Orailoglu
    Computer-Aided Design of Fault-Tolerant VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:88-96 [Journal]
  109. Samuel Norman Hamilton, Alex Orailoglu
    Efficient Self-Recovering ASIC Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:4, pp:25-35 [Journal]
  110. Alex Orailoglu, Alexander V. Veidenbaum
    Guest Editors' Introduction: Application-Specific Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:6-7 [Journal]
  111. Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu
    Seamless Test of Digital Components in Mixed-Signal Paths. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:1, pp:44-55 [Journal]
  112. Sule Ozev, Christian Olgaard, Alex Orailoglu
    Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:82-91 [Journal]
  113. Peter Petrov, Alex Orailoglu
    Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:18-25 [Journal]
  114. Ozgur Sinanoglu, Alex Orailoglu
    Compacting Test Responses for Deeply Embedded SoC Cores. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:4, pp:22-30 [Journal]
  115. Amir K. Hekmatpour, Alex Orailoglu, Paul M. Chau
    Hierarchical Modeling of the VLSI Design Process. [Citation Graph (0, 0)][DBLP]
    IEEE Expert, 1991, v:6, n:2, pp:56-70 [Journal]
  116. Alex Orailoglu
    Guest Editor's Introduction. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2003, v:31, n:6, pp:407-409 [Journal]
  117. Ozgur Sinanoglu, Alex Orailoglu
    Efficient RT-Level Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:166-174 [Journal]
  118. Ozgur Sinanoglu, Alex Orailoglu
    Fast and energy-frugal deterministic test through efficient compression and compaction techniques. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:5, pp:257-266 [Journal]
  119. Alex Orailoglu, Ramesh Karri
    Synthesis of fault-tolerant and real-time microarchitectures. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 1994, v:25, n:1, pp:73-84 [Journal]
  120. Peter Petrov, Alex Orailoglu
    Transforming Binary Code for Low-Power Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:3, pp:21-33 [Journal]
  121. Ozgur Sinanoglu, Alex Orailoglu
    Efficient Construction of Aliasing-Free Compaction Circuitry. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2002, v:22, n:5, pp:82-92 [Journal]
  122. Ismet Bayraktaroglu, Alex Orailoglu
    Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:11, pp:1480-1489 [Journal]
  123. Ismet Bayraktaroglu, Alex Orailoglu
    The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:1, pp:61-75 [Journal]
  124. Alex Orailoglu, Ramesh Karri
    Automatic Synthesis of Self-Recovering VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:2, pp:131-142 [Journal]
  125. Ismet Bayraktaroglu, Alex Orailoglu
    Concurrent test for digital linear systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1132-1142 [Journal]
  126. Laurence Goodby, Alex Orailoglu
    Redundancy and testability in digital filter datapaths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:631-644 [Journal]
  127. Alex Orailoglu
    Microarchitectural synthesis for rapid BIST testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:6, pp:573-586 [Journal]
  128. Peter Petrov, Alex Orailoglu
    Performance and power effectiveness in embedded processors customizable partitioned caches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1309-1318 [Journal]
  129. Peter Petrov, Alex Orailoglu
    Tag compression for low power in dynamically customizable embedded processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1031-1047 [Journal]
  130. Peter Petrov, Alex Orailoglu
    A reprogrammable customization framework for efficient branch resolution in embedded processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:2, pp:452-468 [Journal]
  131. Laurence Goodby, Alex Orailoglu, Paul M. Chau
    Microarchitectural synthesis of performance-constrained, low-power VLSI designs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:122-136 [Journal]
  132. Sule Ozev, Alex Orailoglu
    Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:756-765 [Journal]
  133. Peter Petrov, Alex Orailoglu
    Low-power instruction bus encoding for embedded processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:812-826 [Journal]
  134. Chengmo Yang, Alex Orailoglu
    Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:150-154 [Conf]
  135. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:865-869 [Conf]
  136. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:216-224 [Conf]
  137. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:63-68 [Conf]
  138. Peter Petrov, Alex Orailoglu
    Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2007, v:35, n:2, pp:157-177 [Journal]
  139. Yiorgos Makris, Alex Orailoglu
    On the identification of modular test requirements for low cost hierarchical test path construction. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:315-325 [Journal]
  140. Ozgur Sinanoglu, Alex Orailoglu
    Test power reductions through computationally efficient, decoupled scan chain modifications. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2005, v:54, n:2, pp:215-223 [Journal]
  141. Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu
    Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2004, v:53, n:2, pp:269-278 [Journal]
  142. Alex Orailoglu, Ramesh Karri
    Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:304-311 [Journal]
  143. Samuel Norman Hamilton, Alex Orailoglu
    On-line test for fault-secure fault identification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:446-452 [Journal]
  144. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Towards Nanoelectronics Processor Architectures. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:2-3, pp:235-254 [Journal]

  145. Filtering Global History: Power and Performance Efficient Branch Predictor. [Citation Graph (, )][DBLP]


  146. Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. [Citation Graph (, )][DBLP]


  147. A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization. [Citation Graph (, )][DBLP]


  148. Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions. [Citation Graph (, )][DBLP]


  149. Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules. [Citation Graph (, )][DBLP]


  150. Application specific non-volatile primary memory for embedded systems. [Citation Graph (, )][DBLP]


  151. Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses. [Citation Graph (, )][DBLP]


  152. Miss reduction in embedded processors through dynamic, power-friendly cache design. [Citation Graph (, )][DBLP]


  153. Towards fault tolerant parallel prefix adders in nanoelectronic systems. [Citation Graph (, )][DBLP]


  154. Making DNA self-assembly error-proof: Attaining small growth error rates through embedded information redundancy. [Citation Graph (, )][DBLP]


  155. Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude. [Citation Graph (, )][DBLP]


  156. Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme. [Citation Graph (, )][DBLP]


  157. Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience. [Citation Graph (, )][DBLP]


  158. Processor reliability enhancement through compiler-directed register file peak temperature reduction. [Citation Graph (, )][DBLP]


  159. Metric-based transformations for self testable VLSI designs with high test concurrency. [Citation Graph (, )][DBLP]


  160. Deflecting crosstalk by routing reconsideration through refined signal correlation estimation. [Citation Graph (, )][DBLP]


  161. Performance and energy efficient cache migrationapproach for thermal management in embedded systems. [Citation Graph (, )][DBLP]


  162. Scan power reduction in linear test data compression scheme. [Citation Graph (, )][DBLP]


  163. Power efficient register file update approach for embedded processors. [Citation Graph (, )][DBLP]


  164. Power-Constrained SOC Test Schedules through Utilization of Functional Buses. [Citation Graph (, )][DBLP]


  165. Circuit-level mismatch modelling and yield optimization for CMOS analog circuits. [Citation Graph (, )][DBLP]


  166. Test cost minimization through adaptive test development. [Citation Graph (, )][DBLP]


  167. Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems. [Citation Graph (, )][DBLP]


  168. Architectures for Silicon Nanoelectronics and Beyond. [Citation Graph (, )][DBLP]


  169. Logic Mapping in Crossbar-Based Nanoarchitectures. [Citation Graph (, )][DBLP]


Search in 0.007secs, Finished in 0.767secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002