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Kevin Fan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael S. Schlansker
    A Distributed Control Path Architecture for VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:197-206 [Conf]
  2. Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke
    Systematic Register Bypass Customization for Application-Specific Processors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:64-74 [Conf]
  3. Manjunath Kudlur, Kevin Fan, Michael L. Chu, Scott A. Mahlke
    Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:304-314 [Conf]
  4. Hyunchul Park, Kevin Fan, Manjunath Kudlur, Scott A. Mahlke
    Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:136-146 [Conf]
  5. Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv A. Ravindran, Nathan Clark, Scott A. Mahlke
    FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:201-212 [Conf]
  6. Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke
    Increasing hardware efficiency with multifunction loop accelerators. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:276-281 [Conf]
  7. Manjunath Kudlur, Kevin Fan, Scott A. Mahlke
    Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:270-275 [Conf]
  8. Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke
    Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:219-232 [Conf]
  9. Michael L. Chu, Kevin Fan, Scott A. Mahlke
    Region-based hierarchical operation partitioning for multicluster processors. [Citation Graph (0, 0)][DBLP]
    PLDI, 2003, pp:300-311 [Conf]
  10. Michael L. Chu, Kevin Fan, Rajiv A. Ravindran, Scott A. Mahlke
    Cost-Sensitive Partitioning in an Architecture Synthesis System for Multicluster Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:3, pp:10-20 [Journal]

  11. Edge-centric modulo scheduling for coarse-grained reconfigurable architectures. [Citation Graph (, )][DBLP]


  12. Modulo scheduling for highly customized datapaths to increase hardware reusability. [Citation Graph (, )][DBLP]


  13. DVFS in loop accelerators using BLADES. [Citation Graph (, )][DBLP]


  14. Bridging the computation gap between programmable processors and hardwired accelerators. [Citation Graph (, )][DBLP]


  15. Power-efficient medical image processing using PUMA. [Citation Graph (, )][DBLP]


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