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Scott A. Mahlke: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael S. Schlansker
    A Distributed Control Path Architecture for VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:197-206 [Conf]
  2. Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke
    Systematic Register Bypass Customization for Application-Specific Processors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:64-74 [Conf]
  3. Manjunath Kudlur, Kevin Fan, Michael L. Chu, Scott A. Mahlke
    Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:304-314 [Conf]
  4. Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider
    High-Level Synthesis of Nonprogrammable Hardware Accelerators. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:113-0 [Conf]
  5. David M. Gallagher, William Y. Chen, Scott A. Mahlke, John C. Gyllenhaal, Wen-mei W. Hwu
    Dynamic Memory Disambiguation Using the Memory Conflict Buffer. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1994, pp:183-193 [Conf]
  6. Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
    Sentinel Scheduling for VLIW and Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1992, pp:238-247 [Conf]
  7. Rajeev Krishna, Scott A. Mahlke, Todd M. Austin
    Architectural optimizations for low-power, real-time speech recognition. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:220-231 [Conf]
  8. Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown
    Increasing the number of effective registers in a low-power processor using a windowed register file. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:125-136 [Conf]
  9. Sami Yehia, Nathan Clark, Scott A. Mahlke, Krisztián Flautner
    Exploring the design space of LUT-based transparent accelerators. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:11-21 [Conf]
  10. Hyunchul Park, Kevin Fan, Manjunath Kudlur, Scott A. Mahlke
    Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:136-146 [Conf]
  11. Jason A. Blome, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke
    Cost-efficient soft error protection for embedded microprocessors. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:421-431 [Conf]
  12. Nathan Clark, Amir Hormati, Scott A. Mahlke, Sami Yehia
    Scalable subgraph mapping for acyclic computation accelerators. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:147-157 [Conf]
  13. Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh S. Dasika, Eric D. Marsman, Robert M. Senger, Scott A. Mahlke, Richard B. Brown
    Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache. [Citation Graph (0, 0)][DBLP]
    CGO, 2005, pp:179-190 [Conf]
  14. Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson
    Probabilistic Predicate-Aware Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:151-162 [Conf]
  15. Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson, Hsien-Hsin S. Lee
    Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints. [Citation Graph (0, 0)][DBLP]
    CGO, 2003, pp:169-178 [Conf]
  16. Michael L. Chu, Scott A. Mahlke
    Compiler-directed Data Partitioning for Multicluster Processors. [Citation Graph (0, 0)][DBLP]
    CGO, 2006, pp:208-220 [Conf]
  17. Amir Hormati, Nathan Clark, Scott A. Mahlke
    Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:341-353 [Conf]
  18. Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv A. Ravindran, Nathan Clark, Scott A. Mahlke
    FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:201-212 [Conf]
  19. Rajeev Krishna, Scott A. Mahlke, Todd M. Austin
    Memory system design space exploration for low-power, real-time speech recognition. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:140-145 [Conf]
  20. Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke
    Increasing hardware efficiency with multifunction loop accelerators. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:276-281 [Conf]
  21. Manjunath Kudlur, Kevin Fan, Scott A. Mahlke
    Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:270-275 [Conf]
  22. Roger A. Bringmann, Scott A. Mahlke, Wen-mei W. Hwu
    A study of the effects of compiler-controlled speculation on instruction and data caches. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1995, pp:211-220 [Conf]
  23. Hyunseok Lee, Yuan Lin, Yoav Harel, Mark Woh, Scott A. Mahlke, Trevor N. Mudge, Krisztián Flautner
    Software Defined Radio - A High Performance Embedded Challenge. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:6-26 [Conf]
  24. William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu
    Tolerating First Level Memory Access Latency in High-Performance Systems. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1992, pp:36-43 [Conf]
  25. Scott A. Mahlke, Nancy J. Warter, William Y. Chen, Pohua P. Chang, Wen-mei W. Hwu
    The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1991, pp:142-145 [Conf]
  26. William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu, Tokuzo Kiyohara, Pohua P. Chang
    Tolerating data access latency with register preloading. [Citation Graph (0, 0)][DBLP]
    ICS, 1992, pp:104-113 [Conf]
  27. David I. August, Daniel A. Connors, Scott A. Mahlke, John W. Sias, Kevin M. Crozier, Ben-Chung Cheng, Patrick R. Eaton, Qudus B. Olaniran, Wen-mei W. Hwu
    Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:227-237 [Conf]
  28. David I. August, John W. Sias, Jean-Michel Puiatti, Scott A. Mahlke, Daniel A. Connors, Kevin M. Crozier, Wen-mei W. Hwu
    The Program Decision Logic Approach to Predicated Execution. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:208-219 [Conf]
  29. Nathan Clark, Jason A. Blome, Michael L. Chu, Scott A. Mahlke, Stuart Biles, Krisztián Flautner
    An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:272-283 [Conf]
  30. Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu
    IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:266-275 [Conf]
  31. Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu
    IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:408-417 [Conf]
  32. Tokuzo Kiyohara, Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Sadun Anik, Wen-mei W. Hwu
    Register Connection: A New Approach to Adding Registers into Instruction Set Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:247-256 [Conf]
  33. Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner
    SODA: A Low-power Architecture For Software Radio. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:89-101 [Conf]
  34. Scott A. Mahlke, Richard E. Hank, James E. McCormick, David I. August, Wen-mei W. Hwu
    A Comparison of Full and Partial Predicated Execution Support for ILP Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:138-150 [Conf]
  35. Lakshmi N. Chakrapani, John C. Gyllenhaal, Wen-mei W. Hwu, Scott A. Mahlke, Krishna V. Palem, Rodric M. Rabbah
    Trimaran: An Infrastructure for Research in Instruction-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    LCPC, 2004, pp:32-41 [Conf]
  36. William Y. Chen, Roger A. Bringmann, Scott A. Mahlke, Sadun Anik, Tokuzo Kiyohara, Nancy J. Warter, Daniel M. Lavery, Wen-mei W. Hwu, Richard E. Hank, John C. Gyllenhaal
    Using Profile Information to Assist Advaced Compiler Optimization and Scheduling. [Citation Graph (0, 0)][DBLP]
    LCPC, 1992, pp:31-48 [Conf]
  37. Nathan Clark, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke, Krisztián Flautner
    Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:30-40 [Conf]
  38. Nathan Clark, Hongtao Zhong, Scott A. Mahlke
    Processor Acceleration Through Automated Instruction Set Customization. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:129-140 [Conf]
  39. Santosh G. Abraham, Scott A. Mahlke
    Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:114-125 [Conf]
  40. Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, John C. Gyllenhaal, Wen-mei W. Hwu
    Speculative execution exception recovery using write-back suppression. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:214-223 [Conf]
  41. David I. August, Wen-mei W. Hwu, Scott A. Mahlke
    A Framework for Balancing Control Flow and Predication. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:92-103 [Conf]
  42. Pohua P. Chang, William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu
    Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:25-33 [Conf]
  43. William Y. Chen, Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, James E. Sicolo
    An efficient architecture for loop based data preloading. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:92-101 [Conf]
  44. William Y. Chen, Scott A. Mahlke, Pohua P. Chang, Wen-mei W. Hwu
    Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:69-73 [Conf]
  45. Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke
    Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:219-232 [Conf]
  46. Richard E. Hank, Scott A. Mahlke, Roger A. Bringmann, John C. Gyllenhaal, Wen-mei W. Hwu
    Superblock formation using static program analysis. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:247-255 [Conf]
  47. Scott A. Mahlke, Richard E. Hank, Roger A. Bringmann, John C. Gyllenhaal, David M. Gallagher, Wen-mei W. Hwu
    Characterizing the impact of predicated execution on branch prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:217-227 [Conf]
  48. Scott A. Mahlke, David C. Lin, William Y. Chen, Richard E. Hank, Roger A. Bringmann
    Effective compiler support for predicated execution using the hyperblock. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:45-54 [Conf]
  49. Scott A. Mahlke, Balas K. Natarajan
    Compiler Synthesized Dynamic Branch Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:153-164 [Conf]
  50. Michael L. Chu, Kevin Fan, Scott A. Mahlke
    Region-based hierarchical operation partitioning for multicluster processors. [Citation Graph (0, 0)][DBLP]
    PLDI, 2003, pp:300-311 [Conf]
  51. Michael S. Schlansker, Scott A. Mahlke, Richard Johnson
    Control CPR: A Branch Height Reduction Optimization for EPIC Architectures. [Citation Graph (0, 0)][DBLP]
    PLDI, 1999, pp:155-168 [Conf]
  52. Nancy J. Warter, Scott A. Mahlke, Wen-mei W. Hwu, B. Ramakrishna Rau
    Reverse If-Conversion. [Citation Graph (0, 0)][DBLP]
    PLDI, 1993, pp:290-299 [Conf]
  53. Scott A. Mahlke, William Y. Chen, John C. Gyllenhaal, Wen-mei W. Hwu
    Compiler Code Transformations for Superscalar-Based High Performance Systems. [Citation Graph (0, 0)][DBLP]
    SC, 1992, pp:808-817 [Conf]
  54. Todd M. Austin, David Blaauw, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Wayne Wolf
    Mobile Supercomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:5, pp:81-83 [Journal]
  55. David I. August, Wen-mei W. Hwu, Scott A. Mahlke
    The Partial Reverse If-Conversion Framework for Balancing Control Flow and Predication. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:5, pp:381-423 [Journal]
  56. Nathan Clark, Hongtao Zhong, Wilkin Tang, Scott A. Mahlke
    Automatic Design of Application Specific Instruction Set Extensions Through Dataflow Graph Exploration. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2003, v:31, n:6, pp:429-449 [Journal]
  57. Michael L. Chu, Kevin Fan, Rajiv A. Ravindran, Scott A. Mahlke
    Cost-Sensitive Partitioning in an Architecture Synthesis System for Multicluster Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:3, pp:10-20 [Journal]
  58. Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu
    Profile-guided Automatic Inline Expansion for C Programs. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1992, v:22, n:5, pp:349-369 [Journal]
  59. Pohua P. Chang, Scott A. Mahlke, Wen-mei W. Hwu
    Using Profile Information to Assist Classic Code Optimizations. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1991, v:21, n:12, pp:1301-1321 [Journal]
  60. Pohua P. Chang, Daniel M. Lavery, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu
    The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:3, pp:353-370 [Journal]
  61. Pohua P. Chang, Nancy J. Warter, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu
    Three Architecutral Models for Compiler-Controlled Speculative Execution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:4, pp:481-494 [Journal]
  62. Nathan T. Clark, Hongtao Zhong, Scott A. Mahlke
    Automated Custom Instruction Generation for Domain-Specific Processor Acceleration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:10, pp:1258-1270 [Journal]
  63. Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown
    Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:8, pp:998-1012 [Journal]
  64. Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood
    Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1355-1371 [Journal]
  65. Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
    Sentinel Scheduling for VLIW and Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1993, v:11, n:4, pp:376-408 [Journal]
  66. Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau
    Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:4, pp:752-773 [Journal]
  67. Yuan Lin, Manjunath Kudlur, Scott A. Mahlke, Trevor N. Mudge
    Hierarchical coarse-grained stream compilation for software defined radio. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:115-124 [Conf]
  68. Michael L. Chu, Scott A. Mahlke
    Code and data partitioning for fine-grain parallelism. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:161-164 [Conf]
  69. Rajiv Ravindran, Michael Chu, Scott A. Mahlke
    Compiler-managed partitioned data caches for low power. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:237-247 [Conf]
  70. Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner
    The Next Generation Challenge for Software Defined Radio. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:343-354 [Conf]
  71. Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner
    SODA: A High-Performance DSP Architecture for Software-Defined Radio. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:114-123 [Journal]
  72. Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky
    Architecting a reliable CMP switch architecture. [Citation Graph (0, 0)][DBLP]
    TACO, 2007, v:4, n:1, pp:- [Journal]

  73. Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures. [Citation Graph (, )][DBLP]


  74. Edge-centric modulo scheduling for coarse-grained reconfigurable architectures. [Citation Graph (, )][DBLP]


  75. Shoestring: probabilistic soft error reliability on the cheap. [Citation Graph (, )][DBLP]


  76. MacroSS: macro-SIMDization of streaming applications. [Citation Graph (, )][DBLP]


  77. StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems. [Citation Graph (, )][DBLP]


  78. Optimus: efficient realization of streaming applications on FPGAs. [Citation Graph (, )][DBLP]


  79. CGRA express: accelerating execution using dynamic operation fusion. [Citation Graph (, )][DBLP]


  80. Modulo scheduling for highly customized datapaths to increase hardware reusability. [Citation Graph (, )][DBLP]


  81. Stream Compilation for Real-Time Embedded Multicore Systems. [Citation Graph (, )][DBLP]


  82. DVFS in loop accelerators using BLADES. [Citation Graph (, )][DBLP]


  83. Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors. [Citation Graph (, )][DBLP]


  84. Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping. [Citation Graph (, )][DBLP]


  85. Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications. [Citation Graph (, )][DBLP]


  86. Uncovering hidden loop level parallelism in sequential applications. [Citation Graph (, )][DBLP]


  87. BulletProof: a defect-tolerant CMP switch architecture. [Citation Graph (, )][DBLP]


  88. Bridging the computation gap between programmable processors and hardwired accelerators. [Citation Graph (, )][DBLP]


  89. VEAL: Virtualized Execution Accelerator for Loops. [Citation Graph (, )][DBLP]


  90. AnySP: anytime anywhere anyway signal processing. [Citation Graph (, )][DBLP]


  91. Necromancer: enhancing system throughput by animating dead cores. [Citation Graph (, )][DBLP]


  92. Enabling ultra low voltage system operation by tolerating on-chip cache failures. [Citation Graph (, )][DBLP]


  93. Diet SODA: a power-efficient processor for digital cameras. [Citation Graph (, )][DBLP]


  94. Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures. [Citation Graph (, )][DBLP]


  95. Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures. [Citation Graph (, )][DBLP]


  96. Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications. [Citation Graph (, )][DBLP]


  97. ZerehCache: armoring cache architectures in high defect density technologies. [Citation Graph (, )][DBLP]


  98. Self-calibrating Online Wearout Detection. [Citation Graph (, )][DBLP]


  99. From SODA to scotch: The evolution of a wireless baseband processor. [Citation Graph (, )][DBLP]


  100. The StageNet fabric for constructing resilient multicore systems. [Citation Graph (, )][DBLP]


  101. Gadara: Dynamic Deadlock Avoidance for Multithreaded Programs. [Citation Graph (, )][DBLP]


  102. Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory. [Citation Graph (, )][DBLP]


  103. Orchestrating the execution of stream programs on multicore platforms. [Citation Graph (, )][DBLP]


  104. The theory of deadlock avoidance via discrete control. [Citation Graph (, )][DBLP]


  105. A parameterized dataflow language extension for embedded streaming systems. [Citation Graph (, )][DBLP]


  106. Customizing wide-SIMD architectures for H.264. [Citation Graph (, )][DBLP]


  107. Power-efficient medical image processing using PUMA. [Citation Graph (, )][DBLP]


  108. A dataflow-centric approach to design low power control paths in CGRAs. [Citation Graph (, )][DBLP]


  109. Parade: A versatile parallel architecture for accelerating pulse train clustering. [Citation Graph (, )][DBLP]


  110. Gadara nets: Modeling and analyzing lock allocation for deadlock avoidance in multithreaded software. [Citation Graph (, )][DBLP]


  111. Design and Implementation of Turbo Decoders for Software Defined Radio. [Citation Graph (, )][DBLP]


  112. Analyzing the scalability of SIMD for the next generation software defined radio. [Citation Graph (, )][DBLP]


  113. Eliminating Concurrency Bugs with Control Engineering. [Citation Graph (, )][DBLP]


  114. Mobile Supercomputers for the Next-Generation Cell Phone. [Citation Graph (, )][DBLP]


  115. Reliable Systems on Unreliable Fabrics. [Citation Graph (, )][DBLP]


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