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Bernard Pottier: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. K. Bouazza, Joël Champeau, P. Ng, Bernard Pottier, Stéphane Rubini
    Implementing cellular automata on the ArMen machine. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:317-324 [Conf]
  2. Caaliph Andriamisaina, Catherine Dezan, Christophe Jégo, Bernard Pottier
    Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:263-266 [Conf]
  3. Loïc Lagadec, Dominique Lavenier, Erwan Fabiani, Bernard Pottier
    Placing, Routing, and Editing Virtual FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:357-366 [Conf]
  4. Loïc Lagadec, Bernard Pottier
    A 6200 Model and Editor Based on Object Technology. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:515-519 [Conf]
  5. Joël Champeau, Luc Le Pape, Bernard Pottier, Stéphane Rubini, Eric Gautrin, Laurent Perraudeau
    Flexible Parallel FPGA-Based Architectures with ArMe. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:105-113 [Conf]
  6. Catherine Dezan, Christophe Jégo, Bernard Pottier, Christophe Gouyen, Loïc Lagadec
    The Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA. [Citation Graph (0, 0)][DBLP]
    HICSS, 2006, pp:- [Conf]
  7. Loïc Lagadec, Bernard Pottier, Oscar Villellas, Erwan Fabiani, Catherine Dezan
    A LUT based Approach for High Level Synthesis on FPGAs. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:167-172 [Conf]
  8. Catherine Dezan, Loïc Lagadec, Bernard Pottier
    Object Oriented Approach for Modeling Digital Circuits. [Citation Graph (0, 0)][DBLP]
    MSE, 1999, pp:51-52 [Conf]
  9. Jean Marie Filloque, Eric Gautrin, Bernard Pottier
    Efficient Global Computations on a Processor Network with Programmable Logic. [Citation Graph (0, 0)][DBLP]
    PARLE (1), 1991, pp:69-82 [Conf]
  10. Christophe Gouyen, Loïc Lagadec, Bernard Pottier, A. André, E. Lepicier, François Dupont
    Compiler level integration of a portable CAD framework for reconfigurable circuits. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:19-26 [Conf]
  11. Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys
    Co-Design of Massively Parallel Embedded Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:27-34 [Conf]
  12. Joel Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber, Samar Yazdani
    Compiler and System Techniques for soc Distributed Reconfigurable Accelerators. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:293-302 [Conf]
  13. Erwan Fabiani, Christophe Gouyen, Bernard Pottier
    Intermediate Level Components for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:59-68 [Conf]
  14. L. Lemarchand, A. Plantec, Bernard Pottier, S. Zanati
    An object-oriented environment for specification and concurrent execution of genetic algorithms. [Citation Graph (0, 0)][DBLP]
    OOPS Messenger, 1993, v:4, n:2, pp:163-165 [Journal]
  15. Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier
    Massively Parallel Processor Architectures: A Co-design Approach. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:61-68 [Conf]
  16. Samar Yazdani, Joel Cambonie, Bernard Pottier
    Coordinated concurrent memory accesses on a reconfigurable multimedia processor. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:76-83 [Conf]

  17. Application Analysis for Parallel Processing. [Citation Graph (, )][DBLP]


  18. Application Capturing and Performance Estimation in an Holistic Design Environment. [Citation Graph (, )][DBLP]


  19. An Integrated Platform for Heterogeneous Reconfigurable Computing. [Citation Graph (, )][DBLP]


  20. FPGAs or Distributed Systems? [Citation Graph (, )][DBLP]


  21. A Heuristic (delta, D) Digraph to Interpolate between Hypercube and de Bruijn Topologies for Future On-Chip Interconnection Networks. [Citation Graph (, )][DBLP]


  22. Programming Reconfigurable Decoupled Application Control Accelerator For Mobile Systems. [Citation Graph (, )][DBLP]


  23. Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder. [Citation Graph (, )][DBLP]


  24. Reconfiguralbe multimedia accelerator for mobile systems. [Citation Graph (, )][DBLP]


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