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Constantinos E. Goutis: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dimitrios Soudris, Michael K. Birbas, Constantinos E. Goutis
    Direct mapping of nested loops on piecewise regular processor arrays. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:145-150 [Conf]
  2. Labros Bisdounis, Odysseas G. Koufopavlou, Constantinos E. Goutis, Spiridon Nikolaidis
    Switching Response Modeling of the CMOS Inverter for Sub-micron Devices. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:729-0 [Conf]
  3. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:247-252 [Conf]
  4. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:247-252 [Conf]
  5. Nikolaos D. Liveris, Nikolaos D. Zervas, Dimitrios Soudris, Constantinos E. Goutis
    A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:977-983 [Conf]
  6. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:275-276 [Conf]
  7. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:252- [Conf]
  8. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:868-873 [Conf]
  9. John Ant. Hallas, Evaggelinos P. Mariatos, Michael K. Birbas, Alexios N. Birbas, Constantinos E. Goutis
    A CAD Tool for the Development of an Extra-Fast Fuzzy Logic Controller Based on FPGAs and Memory Modules. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:309-311 [Conf]
  10. Nikolas Kroupis, Minas Dasygenis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, Nikolaos D. Zervas, Constantinos E. Goutis
    Power, performance and area exploration of block matching algorithms mapped on programmable processors. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2001, pp:728-731 [Conf]
  11. Efstathios D. Kyriakis-Bitzaros, Odysseas G. Koufopavlou, Constantinos E. Goutis
    Space-Time Representation of Iterative Algorithms and The Design of Regular Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:2-9 [Conf]
  12. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  13. Grigoris Dimitroulakos, Michalis D. Galanis, Constantinos E. Goutis
    Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  14. Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis
    Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  15. Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis
    Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  16. Chrissavgi Dre, Anna Tatsaki, Thanos Stouraitis, Constantinos E. Goutis
    Alternative Architectures for the 2-D DCT Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2156-2159 [Conf]
  17. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A methodology for partitioning DSP applications in hybrid reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1206-1209 [Conf]
  18. John Ant. Hallas, Michael K. Birbas, Alexios N. Birbas, John C. Kikidis, Constantinos E. Goutis
    Near-Lossless Compression of Continuous-Tone Still Images Using Fuzzy Logic Notions and the Binary Arithmetic Coder (Q-Coder). [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:125-128 [Conf]
  19. Evaggelinos P. Mariatos, D. E. Metafas, John Ant. Hallas, Constantinos E. Goutis
    A Fast DCT Processor, Based on Special Purpose CORDIC Rotators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:271-274 [Conf]
  20. Spiridon Nikolaidis, D. E. Metafas, Constantinos E. Goutis
    CORDIC Based Pipeline Architecture for All-pass Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1917-1920 [Conf]
  21. Dimitrios Soudris, P. D. Georgakopoulos, Constantinos E. Goutis
    A Systematic Methodology for Designing Multilevel Systolic Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1738-1741 [Conf]
  22. Nikolaos D. Zervas, I. Tagopoulos, Vassilis Spiliotopoulos, Giorgos P. Anagnostopoulos, Dimitrios Soudris, Constantinos E. Goutis
    Performance comparison of DWT scheduling alternatives on programmable platforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:761-764 [Conf]
  23. M. Perakis, A. E. Tzimas, E. G. Metaxakis, Dimitrios Soudris, G. A. Kalivas, C. Katis, Chrissavgi Dre, Constantinos E. Goutis, Adonios Thanailakis, Thanos Stouraitis
    The VLSI implementation of a baseband receiver for DECT-based portable applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:198-201 [Conf]
  24. George Theodoridis, S. Theoharis, Dimitrios Soudris, Thanos Stouraitis, Constantinos E. Goutis
    An efficient probabilistic method for logic circuits using real delay gate model. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:286-289 [Conf]
  25. Nikolaos D. Zervas, Kostas Masselos, Odysseas G. Koufopavlou, Constantinos E. Goutis
    Power exploration of multimedia applications realized on embedded cores. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 1999, pp:378-381 [Conf]
  26. Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis
    Low power synthesis of sum-of-product computation in DSP algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:420-423 [Conf]
  27. Athanasios Kakarountas, K. Papadomanolakis, Spiridon Nikolaidis, Dimitrios Soudris, Constantinos E. Goutis
    Confronting violations of the TSCG(T) in low-power design. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:313-316 [Conf]
  28. Kostas Masselos, Koen Danckaert, Francky Catthoor, Constantinos E. Goutis, Hugo De Man
    A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:270-272 [Conf]
  29. Kostas Masselos, S. Theoharis, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis
    Low power synthesis of sum-of-products computation (poster session). [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:234-237 [Conf]
  30. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:652-661 [Conf]
  31. Athanasios Kakarountas, K. Papadomanolakis, V. Kokkinos, Constantinos E. Goutis
    Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:187-194 [Conf]
  32. Athanasios Kakarountas, Vassilis Spiliotopoulos, Spiridon Nikolaidis, Constantinos E. Goutis
    The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:501-509 [Conf]
  33. Dimitris Karatasos, Athanasios Kakarountas, George Theodoridis, Constantinos E. Goutis
    A Novel Constant-Time Fault-Secure Binary Counter. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:742-749 [Conf]
  34. Kostas Masselos, Panagiotis Merakos, Constantinos E. Goutis
    Power Efficient Vector Quantization Design Using Pixel Truncation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:409-418 [Conf]
  35. George Theodoridis, S. Theoharis, Nikolaos D. Zervas, Constantinos E. Goutis
    Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:76-87 [Conf]
  36. Nikolaos D. Zervas, S. Theoharis, Athanasios Kakarountas, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:47-55 [Conf]
  37. Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis
    Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:243-254 [Conf]
  38. Athanasios Milidonis, Grigoris Dimitroulakos, Michalis D. Galanis, George Theodoridis, Constantinos E. Goutis, Francky Catthoor
    An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:122-136 [Conf]
  39. Michalis D. Galanis, Paris Kitsos, Giorgos Kostopoulos, Nicolas Sklavos, Constantinos E. Goutis
    Comparison of the Hardware Implementation of Stream Ciphers. [Citation Graph (0, 0)][DBLP]
    Int. Arab J. Inf. Technol., 2005, v:2, n:4, pp:267-274 [Journal]
  40. Grigoris Dimitroulakos, Michalis D. Galanis, Athanasios Milidonis, Constantinos E. Goutis
    A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:39, n:1, pp:1-11 [Journal]
  41. Odysseas G. Koufopavlou, Constantinos E. Goutis
    Image reconstruction on a special purpose array processor. [Citation Graph (0, 0)][DBLP]
    Image Vision Comput., 1992, v:10, n:7, pp:479-484 [Journal]
  42. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
    A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:877-893 [Journal]
  43. Spiridon Nikolaidis, E. Karaolis, Athanasios Kakarountas, K. Papadomanolakis, Constantinos E. Goutis
    A Methodology for Calculating the Undetectable Double-Faults in Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:1, pp:75-92 [Journal]
  44. Efstathios D. Kyriakis-Bitzaros, Constantinos E. Goutis
    An Efficient Decompostion Technique for Mapping Nested Loops with Constant Dependencies into Regular Processor Arrays. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1992, v:16, n:3, pp:258-264 [Journal]
  45. S. Theoharis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Adonios Thanailakis
    A fast and accurate delay dependent method for switching estimation of large combinational circuits. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2002, v:48, n:4-5, pp:113-124 [Journal]
  46. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
    A high-performance data path for synthesizing DSP kernels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1154-1162 [Journal]
  47. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    Automated framework for partitioning DSP applications in hybrid reconfigurable platforms. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:1, pp:1-14 [Journal]
  48. Athanasios Milidonis, N. Alachiotis, V. Porpodas, Haralambos Michail, Athanasios Kakarountas, Constantinos E. Goutis
    Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:612-617 [Conf]
  49. Grigoris Dimitroulakos, Michalis D. Galanis, Constantinos E. Goutis
    Resource constrained modulo scheduling for coarse-grained reconfigurable arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  50. Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis
    Mapping DSP applications on processor/coarse-grain reconfigurable array architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  51. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  52. Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis
    Novel techniques for bus power consumption reduction in realizations of sum-of-product computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:4, pp:492-497 [Journal]
  53. Koen Danckaert, Kostas Masselos, Francky Catthoor, Hugo De Man, Constantinos E. Goutis
    Strategy for power-efficient design of parallel systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:258-265 [Journal]
  54. Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man
    A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:515-518 [Journal]
  55. Kostas Masselos, Panagiotis Merakos, S. Theoharis, Thanos Stouraitis, Constantinos E. Goutis
    Power efficient data path synthesis of sum-of-products computations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:446-450 [Journal]

  56. A low-power and high-throughput implementation of the SHA-1 hash function. [Citation Graph (, )][DBLP]


  57. An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays. [Citation Graph (, )][DBLP]


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