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Eric Rotenberg: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
    Adaptive Mode Control: A Static-Power-Efficient Cache Design. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:61-0 [Conf]
  2. Karthik Sundaramoorthy, Zachary Purser, Eric Rotenberg
    Slipstream Processors: Improving both Performance and Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2000, pp:257-268 [Conf]
  3. Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy
    Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:83-94 [Conf]
  4. Ali El-Haj-Mahmoud, Ahmed S. Al-Zawawi, Aravindh Anantaraman, Eric Rotenberg
    Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:213-224 [Conf]
  5. Ali El-Haj-Mahmoud, Eric Rotenberg
    Safely exploiting multithreaded processors to tolerate memory latency in real-time systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:2-13 [Conf]
  6. Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg
    A case for dynamic pipeline scaling. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:1-8 [Conf]
  7. Eric Rotenberg
    AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. [Citation Graph (0, 0)][DBLP]
    FTCS, 1999, pp:84-91 [Conf]
  8. Khaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg
    Slipstream Execution Mode for CMP-Based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:179-190 [Conf]
  9. Eric Rotenberg, Quinn Jacobson, James E. Smith
    A Study of Control Independence in Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:115-124 [Conf]
  10. Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Rotenberg
    Tapping ZettaRAMTM for Low-Power Memory Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:83-94 [Conf]
  11. Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller
    Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:350-361 [Conf]
  12. Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan
    A Large, Fast Instruction Window for Tolerating Cache Misses. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:59-70 [Conf]
  13. Erik Jacobsen, Eric Rotenberg, James E. Smith
    Assigning Confidence to Conditional Branch Predictions. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:142-152 [Conf]
  14. Quinn Jacobson, Eric Rotenberg, James E. Smith
    Path-Based Next Trace Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:14-23 [Conf]
  15. Zachary Purser, Karthik Sundaramoorthy, Eric Rotenberg
    A study of slipstream processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:269-280 [Conf]
  16. Eric Rotenberg
    Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:28-39 [Conf]
  17. Eric Rotenberg, Steve Bennett, James E. Smith
    Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:24-35 [Conf]
  18. Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith
    Trace Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:138-148 [Conf]
  19. Eric Rotenberg, James E. Smith
    Control Independence in Trace Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:4-15 [Conf]
  20. Aravindh Anantaraman, Kiran Seth, Eric Rotenberg, Frank Mueller
    Enforcing Safety of Real-Time Schedules on Contemporary Processors Using a Virtual Simple Architecture (VISA). [Citation Graph (0, 0)][DBLP]
    RTSS, 2004, pp:114-125 [Conf]
  21. Kiran Seth, Aravindh Anantaraman, Frank Mueller, Eric Rotenberg
    FAST: Frequency-Aware Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    RTSS, 2003, pp:40-51 [Conf]
  22. Eric Rotenberg, James E. Smith
    Control Independence in Trace Processors. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  23. Jinson Koppanalil, Yuanyuan Yang, Jianchao Wang, Eric Rotenberg
    A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:4, pp:399-413 [Journal]
  24. Eric Rotenberg, Steve Bennett, James E. Smith
    A Trace Cache Microarchitecture and Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:111-120 [Journal]
  25. Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Krishnan Sivasubramanian, Eric Rotenberg
    ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:2, pp:147-160 [Journal]
  26. Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
    Adaptive mode control: A static-power-efficient cache design. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:3, pp:347-372 [Journal]
  27. Kiran Seth, Aravindh Anantaraman, Frank Mueller, Eric Rotenberg
    FAST: Frequency-aware static timing analysis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:200-224 [Journal]
  28. Vimal K. Reddy, Eric Rotenberg
    Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:307-316 [Conf]
  29. Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary
    Transparent control independence (TCI). [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:448-459 [Conf]

  30. Core-Selectability in Chip Multiprocessors. [Citation Graph (, )][DBLP]


  31. EXACT: explicit dynamic-branch prediction with active updates. [Citation Graph (, )][DBLP]


  32. Coverage of a microarchitecture-level fault check regimen in a superscalar processor. [Citation Graph (, )][DBLP]


  33. Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM. [Citation Graph (, )][DBLP]


  34. Architectural Contesting. [Citation Graph (, )][DBLP]


  35. Assertion-Based Microarchitecture Design for Improved Reliability. [Citation Graph (, )][DBLP]


  36. Configurational Workload Characterization. [Citation Graph (, )][DBLP]


  37. The importance of accurate task arrival characterization in the design of processing cores. [Citation Graph (, )][DBLP]


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