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Publications of Author

1. Subhashis Majumder, Bhargab B. Bhattacharya
   Density or Discrepancy: A VLSI Designer's Dilemma in Hot Spot Analysis. [Citation Graph (0, 0)][DBLP]
   CCCG, 2005, pp:167-170 [Conf]
   
2. Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Subhas C. Nandy
   Area(number)-balanced hierarchy of staircase channels with minimum crossing nets. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2001, pp:395-398 [Conf]
   
3. Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya
   Topological Routing Amidst Polygonal Obstacles. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2000, pp:274-279 [Conf]
   
4. Subhashis Majumder, Bhargab B. Bhattacharya
   Solving Thermal Problems of Hot Chips Using Voronoi Diagrams. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2006, pp:545-548 [Conf]
   
5. Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal
   Path Delay Testing: Variable-Clock Versus Rated-Clock. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1998, pp:470-475 [Conf]
   
6. Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell
   A Complete Characterization of Path Delay Faults through Stuck-at Faults. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1999, pp:492-497 [Conf]
   
7. Subhashis Majumder, Subhas C. Nandy, Bhargab B. Bhattacharya
   Partitioning VLSI Floorplans by Staircase Channels for Global Routing. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1998, pp:59-64 [Conf]
   
8. Subhashis Majumder, Susmita Sur-Kolay, Subhas C. Nandy, Bhargab B. Bhattacharya, B. Chakraborty
   Hot Spots and Zones in a Chip: A Geometrician's View. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2005, pp:691-696 [Conf]
   
9. Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell
   On Delay-Untestable Paths and Stuck-Fault Redundancy. [Citation Graph (0, 0)][DBLP]
   VTS, 1998, pp:194-199 [Conf]
   
10. Subhashis Majumder, Subhas C. Nandy, Bhargab B. Bhattacharya
    On Finding A Staircase Channel With Minimum Crossing Nets In A VLSI Floorplan. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2004, v:13, n:5, pp:1019-1038 [Journal]
    
11. Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell
    A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2004, v:19, n:6, pp:955-964 [Journal]
    
12. Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das
    Hierarchical partitioning of VLSI floorplans by staircases. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:1, pp:- [Journal]