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Carlos Augusto Paiva da Silva Martins: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Christiane V. Pousa, Luís Fabrício Wanderley Góes, Carlos Augusto Paiva da Silva Martins
    Reconfigurable consistency model for object-based software DSM. [Citation Graph (0, 0)][DBLP]
    CCGRID, 2005, pp:937-944 [Conf]
  2. Luís Fabrício Wanderley Góes, Luiz Eduardo da Silva Ramos, Carlos Augusto Paiva da Silva Martins
    ClusterSim: a Java-based parallel discrete-event simulation tool for cluster computing. [Citation Graph (0, 0)][DBLP]
    CLUSTER, 2004, pp:401-410 [Conf]
  3. Luís Fabrício Wanderley Góes, Christiane V. Pousa, Milene Barbosa Carvalho, Luiz Eduardo da Silva Ramos, Carlos Augusto Paiva da Silva Martins
    JSDESLib: A Library for the Development of Discrete-Event Simulation Tools of Parallel Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  4. Christiane V. Pousa, Luís Fabrício Wanderley Góes, Carlos Augusto Paiva da Silva Martins
    Reconfigurable Object Consistency Model. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  5. Christiane V. Pousa, Luís Fabrício Wanderley Góes, Dulcinéia Oliveira da Penha, Carlos Augusto Paiva da Silva Martins
    Reconfigurable Sequential Consistency Algorithm. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  6. Milene Barbosa Carvalho, Luís Fabrício Wanderley Góes, Carlos Augusto Paiva da Silva Martins
    Dynamically reconfigurable cache architecture using adaptive block allocation policy. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  7. Raphael Fonte Boa, Alexandre Marques Amaral, Dulcinéia Oliveira da Penha, Carlos Augusto Paiva da Silva Martins, Petr Ekel
    Parallel Image Segmentation in Reconfigurable Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISPA Workshops, 2006, pp:728-737 [Conf]
  8. Raphael Fonte Boa, Dulcinéia Oliveira da Penha, Alexandre Marques Amaral, Márcio Oliveira Soares de Souza, Carlos Augusto Paiva da Silva Martins, Petr Yakovlevitch Ekel
    RCMP: A Reconfigurable Chip-Multiprocessor Architecture. [Citation Graph (0, 0)][DBLP]
    ISPA Workshops, 2006, pp:94-103 [Conf]
  9. Elton F. D. Nogueira, Luiz J. C. Rocha, Alexei Manso Correa Machado, Carlos A. Pietrobon, Carlos Augusto Paiva da Silva Martins, Rose M. S. Batalha, Petr Ekel
    A Parallel Implementation of the Finite Volume Method for the Simulation of the Natural Convection in a Closed Cavity. [Citation Graph (0, 0)][DBLP]
    ISPA Workshops, 2006, pp:748-757 [Conf]
  10. Christiane V. Pousa, Luís Fabrício Wanderley Góes, Carlos Augusto Paiva da Silva Martins
    Reconfigurable Object Consistency Model for Distributed Shared Memory. [Citation Graph (0, 0)][DBLP]
    ISPA, 2005, pp:132-138 [Conf]
  11. Luiz Eduardo da Silva Ramos, Carlos Augusto Paiva da Silva Martins
    A Proposal of Reconfigurable MPI Collective Communication Functions. [Citation Graph (0, 0)][DBLP]
    ISPA, 2005, pp:102-107 [Conf]
  12. Luís Fabrício Wanderley Góes, Carlos Augusto Paiva da Silva Martins
    Reconfigurable Gang Scheduling Algorithm. [Citation Graph (0, 0)][DBLP]
    JSSPP, 2004, pp:81-101 [Conf]
  13. Milene Barbosa Carvalho, Alexandre Marques Amaral, Luiz Eduardo da Silva Ramos, Carlos Augusto Paiva da Silva Martins, Petr Ekel
    Artificial Neural Network Engine: Parallel and Parameterized Architecture Implemented in FPGA. [Citation Graph (0, 0)][DBLP]
    PReMI, 2005, pp:294-299 [Conf]
  14. Luís Fabrício Wanderley Góes, Luiz Eduardo da Silva Ramos, Carlos Augusto Paiva da Silva Martins
    Performance Analysis of Parallel Programs Using Prober as a Single Aid Tool. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:204-211 [Conf]
  15. Gustavo Nunes Coelho Fantini, Carlos Augusto Paiva da Silva Martins
    A Configurable and Portable Benchmark for 3D Graphics. [Citation Graph (0, 0)][DBLP]
    SIBGRAPI, 2001, pp:375- [Conf]
  16. Henrique C. Freitas, Milene Barbosa Carvalho, Alexandre Marques Amaral, Amanda R. M. Diniz, Carlos Augusto Paiva da Silva Martins, Luiz Eduardo da Silva Ramos
    Reconfigurable crossbar switch architecture for network processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

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