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Publications of Author

1. Tezaswi Raja, Manish Parashar
   Using a Jini based desktop Grid for test vector compaction and a refined economic model. [Citation Graph (0, 0)][DBLP]
   CCGRID, 2004, pp:798-805 [Conf]
   
2. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
   Design of Variable Input Delay Gates for Low Dynamic Power Circuits. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2005, pp:436-445 [Conf]
   
3. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
   Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2003, pp:527-532 [Conf]
   
4. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
   A Tuturial on the Emerging Nanotechnology Devices. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2004, pp:343-360 [Conf]
   
5. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
   CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2004, pp:1035-1040 [Conf]
   
6. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
   Variable Input Delay CMOS Logic for Low Power Design. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2005, pp:598-605 [Conf]
   
7. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
   Transistor Sizing of Logic Gates to Maximize Input Delay Variability. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:1, pp:121-128 [Journal]
   
8. 
   Digital Logic Implementation in Memristor-Based Crossbars - A Tutorial. [Citation Graph (, )][DBLP]