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Hussain Al-Asaad: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hussain Al-Asaad, Ganesh Valliappan, Lourdes Ramirez
    A Novel Functional Testing and Verification Technique for Logic Circuits. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:129-135 [Conf]
  2. Hector Arteaga, Hussain Al-Asaad
    On Increasing the Observability of Modern Microprocessors. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:91-96 [Conf]
  3. Ahmed Sayed, Hussain Al-Asaad
    Survey and Evaluation of Low-Power Flip-Flops. [Citation Graph (0, 0)][DBLP]
    CDES, 2006, pp:77-83 [Conf]
  4. Hector Arteaga, Hussain Al-Asaad
    Approaches for Monitoring Vectors on Microprocessor Buses. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:393-398 [Conf]
  5. Ahmed Sayed, Hussain Al-Asaad
    Survey and Evaluation of Low-Power Full-Adder Cells. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:332-338 [Conf]
  6. Hussain Al-Asaad, Elias S. Manolakos
    A Two-Phase Reconfiguration Strategy for Extracting Linear Arrays Out of Two-Dimensional Architectures. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:56-63 [Conf]
  7. Hussain Al-Asaad, John P. Hayes
    Design verification via simulation and automatic test pattern generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:174-180 [Conf]
  8. Hussain Al-Asaad, Mankuan Michael Vai, James Feldman
    Distributed Reconfiguration of Fault Tolerant VLSI Mulipipeline Arrays with Constant Interstage Path Lengths. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:75-78 [Conf]
  9. Jorge Campos, Hussain Al-Asaad
    Circuit Profiling Mechanisms for High-Level {ATPG}. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:9-14 [Conf]
  10. Jorge Campos, Hussain Al-Asaad
    Search-Space Optimizations for High-Level ATPG. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:84-89 [Conf]
  11. Hussain Al-Asaad, Alireza Sarvi
    Fault Tolerance for Multiprocessor Systems Via Time Redundant Task Scheduling. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:51-57 [Conf]
  12. Hussain Al-Asaad, John P. Hayes
    ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:221-230 [Conf]
  13. Hussain Al-Asaad
    EGFC: An exact global fault collapsing tool for combinational circuits. [Citation Graph (0, 0)][DBLP]
    Circuits, Signals, and Systems, 2005, pp:56-61 [Conf]
  14. Hussain Al-Asaad, Brian T. Murray, John P. Hayes
    Online BIST for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:4, pp:17-24 [Journal]
  15. David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown
    High-level design verification of microprocessors via error modeling. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:581-599 [Journal]
  16. Ahmed Sayed, Hussain Al-Asaad
    A New Statistical Approach for Glitch Estimation in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1641-1644 [Conf]

  17. Efficient Global Fault Collapsing for Combinational Library Modules. [Citation Graph (, )][DBLP]


  18. Low Power Methodologies and Challenges for PWM DC-DC Converters. [Citation Graph (, )][DBLP]


  19. Detection and Isolation of Faulty Processors in Multiprocessor Systems via TMR-Based Time Redundant Task Scheduling. [Citation Graph (, )][DBLP]


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