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Jaafar Alghazo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jaafar Alghazo
    Modeling and Realization of the Floating Point Inverse Square Root, Square Root, and Division unit (fP ISD) Using VHDL and FPGAs. [Citation Graph (0, 0)][DBLP]
    CDES, 2006, pp:39-45 [Conf]
  2. Jaafar Alghazo, Nazeih Botros
    Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAs. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:136-142 [Conf]
  3. Nazeih Botros, Adil Akaaboune, Jaafar Alghazo
    Modeling and Realization of the Human Growth Hormone Secretion Mechanism using VHDL and FPGAs. [Citation Graph (0, 0)][DBLP]
    Modelling, Simulation, and Optimization, 2003, pp:13-18 [Conf]
  4. Adil Akaaboune, Nazeih Botros, Jaafar Alghazo
    Tag Skipping Technique Using WTS Buffer for Optimal Low Power Cache Design. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:13-18 [Conf]
  5. Jaafar Alghazo, Adil Akaaboune, Nazeih Botros
    SF-LRU Cache Replacement Algorithm. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:19-24 [Conf]

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