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Nazeih Botros :
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Jaafar Alghazo , Nazeih Botros Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAs. [Citation Graph (0, 0)][DBLP ] CDES, 2005, pp:136-142 [Conf ] Nagm Mohamed , Nazeih Botros , Wei Zhang The Impact of Cache Organization in Optimizing Microprocessor Power Consumption. [Citation Graph (0, 0)][DBLP ] CDES, 2006, pp:84-90 [Conf ] Nazeih Botros , Adil Akaaboune , Jaafar Alghazo Modeling and Realization of the Human Growth Hormone Secretion Mechanism using VHDL and FPGAs. [Citation Graph (0, 0)][DBLP ] Modelling, Simulation, and Optimization, 2003, pp:13-18 [Conf ] Adil Akaaboune , Nazeih Botros , Jaafar Alghazo Tag Skipping Technique Using WTS Buffer for Optimal Low Power Cache Design. [Citation Graph (0, 0)][DBLP ] MTDT, 2004, pp:13-18 [Conf ] Jaafar Alghazo , Adil Akaaboune , Nazeih Botros SF-LRU Cache Replacement Algorithm. [Citation Graph (0, 0)][DBLP ] MTDT, 2004, pp:19-24 [Conf ] EPIC: An Energy Exploitative Architecture. [Citation Graph (, )][DBLP ] Cache Memory Energy Exploitation in VLIW Architectures. [Citation Graph (, )][DBLP ] Search in 0.001secs, Finished in 0.001secs