The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Nazeih Botros: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jaafar Alghazo, Nazeih Botros
    Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAs. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:136-142 [Conf]
  2. Nagm Mohamed, Nazeih Botros, Wei Zhang
    The Impact of Cache Organization in Optimizing Microprocessor Power Consumption. [Citation Graph (0, 0)][DBLP]
    CDES, 2006, pp:84-90 [Conf]
  3. Nazeih Botros, Adil Akaaboune, Jaafar Alghazo
    Modeling and Realization of the Human Growth Hormone Secretion Mechanism using VHDL and FPGAs. [Citation Graph (0, 0)][DBLP]
    Modelling, Simulation, and Optimization, 2003, pp:13-18 [Conf]
  4. Adil Akaaboune, Nazeih Botros, Jaafar Alghazo
    Tag Skipping Technique Using WTS Buffer for Optimal Low Power Cache Design. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:13-18 [Conf]
  5. Jaafar Alghazo, Adil Akaaboune, Nazeih Botros
    SF-LRU Cache Replacement Algorithm. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:19-24 [Conf]

  6. EPIC: An Energy Exploitative Architecture. [Citation Graph (, )][DBLP]


  7. Cache Memory Energy Exploitation in VLIW Architectures. [Citation Graph (, )][DBLP]


Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002