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José G. Delgado-Frias: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Daniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias
    Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:28-34 [Conf]
  2. Jin Liu, José G. Delgado-Frias
    DAMQ Self-Compacting Buffer Schemes for Systems with Network-On-Chip. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:97-103 [Conf]
  3. Mitchell J. Myjak, José G. Delgado-Frias
    A Symmetric Differential Clock Generator for Bit-Serial Hardware. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:159-164 [Conf]
  4. Suryanarayana Tatapudi, José G. Delgado-Frias
    A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:191-197 [Conf]
  5. Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias
    A Distributed FIFO Scheme for System on Chip Inter-Component Communication. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:536-540 [Conf]
  6. Andy Widjaja, José G. Delgado-Frias
    An H-Tree Based Configuration Scheme for Reconfigurable DSP Hardware. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:530-535 [Conf]
  7. Mitchell J. Myjak, Fredrick L. Anderson, José G. Delgado-Frias
    H-Tree Interconnection Structure for Reconfigurable DSP Hardware. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:170-176 [Conf]
  8. Daniel G. Rice, José G. Delgado-Frias, Douglas H. Summerville
    A Pattern-Associative Router for Interconnection Network Adaptive Algorithms. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. I, 1996, pp:213-217 [Conf]
  9. José G. Delgado-Frias, Richard Diaz
    A VLSI Self-Compacting Buffer for DAMQ Communication Switches. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:128-133 [Conf]
  10. José G. Delgado-Frias, Jabulani Nyathi
    A VLSI High-Performance Encoder with Priority Lookahead. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:59-64 [Conf]
  11. José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan
    A wave-pipelined router architecture using ternary associative memory. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:67-70 [Conf]
  12. José G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville
    A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:246-251 [Conf]
  13. José G. Delgado-Frias, Girish B. Ratanpal
    A VLSI wrapped wave front arbiter for crossbar switches. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:85-88 [Conf]
  14. Adger E. Harvin III, José G. Delgado-Frias
    A Dictionary Machine Emulation on a VLSI Computing Tree System. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:134-139 [Conf]
  15. Robert H. Payne, José G. Delgado-Frias
    MPU: A N-Tuple Matching Processor. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:225-228 [Conf]
  16. José G. Delgado-Frias, D. M. Green
    BVE: a wafer-scale engine for differential equation computation. [Citation Graph (0, 0)][DBLP]
    ICS, 1988, pp:101-107 [Conf]
  17. Mitchell J. Myjak, José G. Delgado-Frias
    Pipelined Multipliers for Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  18. Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis
    A High Performance Pattern Associative Oblivious Router for Tree Topologies. [Citation Graph (0, 0)][DBLP]
    IPPS, 1994, pp:541-545 [Conf]
  19. Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias
    A distributed FIFO scheme for on chip communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1851-1854 [Conf]
  20. Suryanarayana Tatapudi, José G. Delgado-Frias
    A High Performance Hybrid Wave-Pipelined Multiplier. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:282-283 [Conf]
  21. Victor A. Skormin, José G. Delgado-Frias, Dennis L. McGee, Joseph Giordano, Leonard J. Popyack, Vladimir I. Gorodetski, Alexander O. Tarakanov
    BASIS: A Biological Approach to System Information Security. [Citation Graph (0, 0)][DBLP]
    MMM-ACNS, 2001, pp:127-142 [Conf]
  22. Valentine C. Aikens II, Steven M. Barber, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis
    A Neuro-Architecture with Embedded Learning. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Systems, 1995, pp:103-106 [Conf]
  23. Daniel G. Rice, José G. Delgado-Frias, Douglas H. Summerville
    A Pattern-Associative Router for Adaptive Algorithms in Hypercube Networks. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Systems, 1995, pp:238-242 [Conf]
  24. Adger E. Harvin III, José G. Delgado-Frias
    A VLSI-Processing and Communicating Pipelined Tree for Parallel Computing. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Systems, 1995, pp:455-458 [Conf]
  25. J. Park, Brian W. O'Krafka, Stamatis Vassiliadis, José G. Delgado-Frias
    Design and evaluation of a DAMQ multiprocessor network with self-compacting buffers. [Citation Graph (0, 0)][DBLP]
    SC, 1994, pp:713-722 [Conf]
  26. Fred L. Anderson IV, José G. Delgado-Frias
    A Reconfigurable Switch for a DSP Array. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:3-6 [Conf]
  27. Daniel R. Blum, José G. Delgado-Frias
    A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:58-64 [Conf]
  28. Mitchell J. Myjak, José G. Delgado-Frias
    A Two-Level Reconfigurable Architecture for Digital Signal Processing. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:21-27 [Conf]
  29. Li Zhao, José G. Delgado-Frias
    On Throughput of Multipath Data Transmission over Multihop Ad Hoc Networks. [Citation Graph (0, 0)][DBLP]
    Wireless and Optical Communications, 2006, pp:- [Conf]
  30. Laurence Tianruo Yang, José G. Delgado-Frias, Yiming Li, Mohammed Niamat, Dimitrios Soudris, Srinivasa Vemuru
    Preface. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:61- [Journal]
  31. Ming Zhang, Stamatis Vassiliadis, José G. Delgado-Frias
    Sigmoid Generators for Neural Computing Using Piecewise Approximations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:9, pp:1045-1049 [Journal]
  32. Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis
    A Flexible Bit-Pattern Associative Router for Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1996, v:7, n:5, pp:477-485 [Journal]
  33. Douglas H. Summerville, José G. Delgado-Frias
    Approaches for determining dynamic synchronization resource requirements. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 1998, pp:385-388 [Conf]
  34. Daniel R. Blum, José G. Delgado-Frias
    Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2786-2789 [Conf]
  35. Suryanarayana Tatapudi, José G. Delgado-Frias
    A mesochronous pipeline scheme for high performance low power digital systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  36. Mitchell J. Myjak, José G. Delgado-Frias
    Superpipelined reconfigurable hardware for DSP. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  37. H. Lui, José G. Delgado-Frias, Sirisha Medidi
    Using a two-timer scheme to detect selfish nodes in mobile ad-hoc networks. [Citation Graph (0, 0)][DBLP]
    Communications, Internet, and Information Technology, 2007, pp:181-186 [Conf]
  38. H. Lin, José G. Delgado-Frias, Sirisha Medidi
    Using a cache scheme to detect selfish nodes in mobile ad hoc networks. [Citation Graph (0, 0)][DBLP]
    Communications, Internet, and Information Technology, 2007, pp:61-66 [Conf]
  39. R. Guo, José G. Delgado-Frias
    A novel compaction scheme for routing tables in TCAM to enhance cache hit rate. [Citation Graph (0, 0)][DBLP]
    Communications, Internet, and Information Technology, 2007, pp:210-215 [Conf]
  40. Rongsen He, José G. Delgado-Frias
    Interleaved Multistage Switching Fabrics for Scalable High Performance Routers. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]
  41. Rongsen He, José G. Delgado-Frias
    Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:12, pp:1727-1739 [Journal]

  42. FPGA Schemes with Optimized Routing for the Advanced Encryption Standard. [Citation Graph (, )][DBLP]


  43. Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures. [Citation Graph (, )][DBLP]


  44. High-performance low-power AND and Sense-Amp address decoders with selective precharging. [Citation Graph (, )][DBLP]


  45. Redundant Array of Independent Fabrics - An Architecture for Next Generation Network. [Citation Graph (, )][DBLP]


  46. MARS: Misbehavior Detection in Ad Hoc Networks. [Citation Graph (, )][DBLP]


  47. Using a Cache Scheme to Detect Misbehaving Nodes in Mobile Ad-Hoc Networks. [Citation Graph (, )][DBLP]


  48. A Clustering and Genetic Scheme for Large Tsp Optimization Problems. [Citation Graph (, )][DBLP]


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