The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Yung-Yuan Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin
    Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    CDES, 2006, pp:196-202 [Conf]
  2. Yung-Yuan Chen, Kun-Feng Chen
    Incorporating Signature-Monitoring Technique in VLIW Processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:395-402 [Conf]
  3. Yung-Yuan Chen, Shi-Jinn Horng, Hung-Chuan Lai
    An Integrated Fault-Tolerant Design Framework for VLIW Processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:555-562 [Conf]
  4. Yung-Yuan Chen
    Concurrent Detection of Processor Control Errors by Hybrid Signature Monitoring. [Citation Graph (0, 0)][DBLP]
    EDCC, 1999, pp:437-454 [Conf]
  5. Yung-Yuan Chen, Ching-Hwa Cheng, Yung-Ci Chou
    An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:421-438 [Conf]
  6. Yung-Yuan Chen, Kuen-Long Leu, Chao-Sung Yeh
    Fault-Tolerant VLIW Processor Design and Error Coverage Analysis. [Citation Graph (0, 0)][DBLP]
    EUC, 2006, pp:754-765 [Conf]
  7. Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen
    An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:349-354 [Conf]
  8. Yung-Yuan Chen
    Concurrent Detection of Control Flow Errors by Hybrid Signature Monitoring. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:10, pp:1298-1313 [Journal]
  9. Yung-Yuan Chen, Shambhu J. Upadhyaya
    Reliability, Reconfiguration, and Spare Allocation Issues in Binary-Tree Architectures Based on Multiple-Level Redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:6, pp:713-723 [Journal]
  10. Yung-Yuan Chen, Shambhu J. Upadhyaya
    Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:9, pp:1136-1141 [Journal]
  11. Yung-Yuan Chen, Shambhu J. Upadhyaya
    Modeling the Reliability of a Class of Fault-Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:6, pp:737-748 [Journal]
  12. Yung-Yuan Chen, Shambhu J. Upadhyaya, Ching-Hwa Cheng
    A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:12, pp:1363-1371 [Journal]

  13. An Online Control Flow Check for VLIW Processor. [Citation Graph (, )][DBLP]


  14. SoC-level risk assessment using FMEA approach in system design with SystemC. [Citation Graph (, )][DBLP]


  15. Robustness investigation of the FlexRay system. [Citation Graph (, )][DBLP]


  16. An Estimation Model of Vulnerability for Embedded Microprocessors. [Citation Graph (, )][DBLP]


  17. System-Bus Fault Injection Framework in SystemC Design Platform. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.003secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002