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Jiann S. Yuan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jiann S. Yuan, Jia Di
    Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:218-223 [Conf]
  2. Jia Di, Jiann S. Yuan
    Power-aware pipelined multiplier design based on 2-dimensional pipeline gating. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:64-67 [Conf]
  3. Jiann S. Yuan
    Overview of SiGe Technology Modeling and Application. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:67-72 [Conf]
  4. Jia Di, Jiann S. Yuan, Ronald F. DeMara
    High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:260-261 [Conf]
  5. Jia Di, Jiann S. Yuan, Ronald F. DeMara
    Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:2, pp:90-112 [Journal]
  6. Scott C. Smith, Ronald F. DeMara, Jiann S. Yuan, D. Ferguson, D. Lamb
    Optimization of NULL convention self-timed circuits. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:37, n:3, pp:135-165 [Journal]
  7. Scott C. Smith, Ronald F. DeMara, Jiann S. Yuan, M. Hagedorn, D. Ferguson
    Delay-insensitive gate-level pipelining. [Citation Graph (0, 0)][DBLP]
    Integration, 2001, v:30, n:2, pp:103-131 [Journal]
  8. Jia Di, Jiann S. Yuan
    Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:201-216 [Journal]

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