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Publications of Author

1. Jiann S. Yuan, Jia Di
   Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers. [Citation Graph (0, 0)][DBLP]
   CDES, 2005, pp:218-223 [Conf]
   
2. Jia Di, D. P. Vasudevan
   Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays. [Citation Graph (0, 0)][DBLP]
   DELTA, 2006, pp:149-156 [Conf]
   
3. Jia Di, Parag K. Lala, D. P. Vasudevan
   On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. [Citation Graph (0, 0)][DBLP]
   DFT, 2005, pp:371-379 [Conf]
   
4. Jia Di, Jiann S. Yuan
   Power-aware pipelined multiplier design based on 2-dimensional pipeline gating. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2003, pp:64-67 [Conf]
   
5. Jia Di, Jiann S. Yuan, Ronald F. DeMara
   High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2003, pp:260-261 [Conf]
   
6. Jia Di, Fengwei Yang
   D3L - A framework on fighting against non-invasive attacks to integrated circuits for security applications. [Citation Graph (0, 0)][DBLP]
   Circuits, Signals, and Systems, 2005, pp:73-78 [Conf]
   
7. Jia Di, Jiann S. Yuan, Ronald F. DeMara
   Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design. [Citation Graph (0, 0)][DBLP]
   Integration, 2006, v:39, n:2, pp:90-112 [Journal]
   
8. Jia Di, Jiann S. Yuan
   Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2006, v:2, n:2, pp:201-216 [Journal]
   
9. Jia Di, Parag K. Lala
   Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems. [Citation Graph (0, 0)][DBLP]
   J. Electronic Testing, 2007, v:23, n:2-3, pp:175-192 [Journal]
   
10. 
    Delay-Insensitive Ternary Logic. [Citation Graph (, )][DBLP]
    
    
11. 
    Ownership Transfer of RFID Tags based on Electronic Fingerprint. [Citation Graph (, )][DBLP]
    
    
12. 
    Glitch-free design for multi-threshold CMOS NCL circuits. [Citation Graph (, )][DBLP]
    
    
13. 
    Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. [Citation Graph (, )][DBLP]