The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Michel Dubois: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Michel Dubois, Christoph Scheurich, Faye A. Briggs
    Synchronization, Coherence, and Event Ordering in Multiprocessors. [Citation Graph (2, 0)][DBLP]
    IEEE Computer, 1988, v:21, n:2, pp:9-21 [Journal]
  2. Michel Dubois, Faye A. Briggs
    Performance of Synchronized Iterative Processes in Multiprocessor Systems. [Citation Graph (1, 0)][DBLP]
    IEEE Trans. Software Eng., 1982, v:8, n:4, pp:419-431 [Journal]
  3. Martin Kämpe, Per Stenström, Michel Dubois
    Self-correcting LRU replacement policies. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:181-191 [Conf]
  4. Nasir Mohyuddin, Rashed Bhatti, Michel Dubois
    Controlling leakage power with the replacement policy in slumberous caches. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:161-170 [Conf]
  5. Michel Dubois
    Fighting the memory wall with assisted execution. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:168-180 [Conf]
  6. Jaeheon Jeong, Per Stenström, Michel Dubois
    Simple penalty-sensitive replacement policies for caches. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2006, pp:341-352 [Conf]
  7. Aydin Üresin, Michel Dubois
    Generalized Asynchronous Iterations. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1986, pp:272-278 [Conf]
  8. Fong Pong, Andreas Nowatzyk, Gunes Aybay, Michel Dubois
    Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1995, pp:287-300 [Conf]
  9. Koray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois
    The Design of RPM: An FPGA-based Multiprocessor Emulator. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:60-66 [Conf]
  10. Jaeheon Jeong, Michel Dubois
    Cost-Sensitive Cache Replacement Algorithms. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:327-0 [Conf]
  11. Martin Kämpe, Per Stenström, Michel Dubois
    The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:223-232 [Conf]
  12. Xiaogang Qiu, Michel Dubois
    Towards Virtually-Addressed Memory Hierarchies. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:51-62 [Conf]
  13. Adrian Moga, Michel Dubois
    The Effectiveness of SRAM Network Caches in Clustered DSMs. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:103-112 [Conf]
  14. Christoph Scheurich, Michel Dubois
    Dynamic Page Migration in Multiprocessors with Distributed Global Memory. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1988, pp:162-169 [Conf]
  15. KangWoo Lee, Woo-Jong Han, Michel Dubois
    Bottleneck-Free Interconnect and IO Subsystem in SPAX. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1997, pp:524-533 [Conf]
  16. Luiz André Barroso, Michel Dubois
    Cache Coherence on a Slotted Ring. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:230-237 [Conf]
  17. Fredrik Dahlgren, Michel Dubois, Per Stenström
    Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:56-63 [Conf]
  18. Michel Dubois
    A Cache-Based Multiprocessor with High Efficiency. [Citation Graph (0, 0)][DBLP]
    ICPP, 1985, pp:646-648 [Conf]
  19. Michel Dubois
    Effect of Invalidations on the Hit Ratio of Cache-Based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:255-257 [Conf]
  20. Michel Dubois, Faye A. Briggs, Indira Patil, Meera Balakrishnan
    Trace-Driven Simulations of Parallel and Distributed Algorithms in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:909-916 [Conf]
  21. Michel Dubois, Jin-Chin Wang
    Shared Data Contention in a Cache Coherence Protocol. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:146-155 [Conf]
  22. Anastasios A. Economides, Michel Dubois
    Transient Models of Bus-Based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:153-160 [Conf]
  23. Adrian Moga, Michel Dubois, Alain Gefflaut
    Hardware Versus Software Implementation of COMA. [Citation Graph (0, 0)][DBLP]
    ICPP, 1997, pp:248-256 [Conf]
  24. Sharad Mehrotra, Chien-Ming Cheng, Kai Hwang, Michel Dubois, Dhabaleswar K. Panda
    Algorithm-Driven Simulation and Performance Projection of a RISC-based Orthogonal Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1990, pp:244-253 [Conf]
  25. Fong Pong, Per Stenström, Michel Dubois
    An Integrated Methodology for the Verification of Directory-Based Cache Protocols. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:158-165 [Conf]
  26. Christoph Scheurich, Michel Dubois
    Concurrent Miss Resolution in Multiprocessor Caches. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:118-125 [Conf]
  27. Jonas Skeppstedt, Michel Dubois
    Hybrid compiler/hardware prefetching for multiprocessors using low-overhead cache miss traps. [Citation Graph (0, 0)][DBLP]
    ICPP, 1997, pp:298-305 [Conf]
  28. Aydin Üresin, Michel Dubois
    Asynchronous Relaxation of Non-Numerical Data. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:499-501 [Conf]
  29. Aydin Üresin, Michel Dubois
    Asynchronous Iterations with Bounded Delay. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1990, pp:236-243 [Conf]
  30. Jin-Chin Wang, Michel Dubois, Faye A. Briggs
    Analytical Modeling for Finite Cache Effects. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:287-291 [Conf]
  31. Kai Hwang, Michel Dubois, Dhabaleswar K. Panda, S. Rao, Shisheng Shang, Aydin Üresin, W. Mao, H. Nair, M. Lytwyn, F. Hsieh, J. Liu, Sharad Mehrotra, Chien-Ming Cheng
    OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses. [Citation Graph (0, 0)][DBLP]
    ICS, 1990, pp:7-22 [Conf]
  32. Koray Öner, Michel Dubois
    Effects of Memory Latencies on Non-Blocking Processor/Cache Architectures. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1993, pp:338-347 [Conf]
  33. Yung-Syau Chen, Michel Dubois
    Cache Protocols with Partial Block Invalidations. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:16-23 [Conf]
  34. Ashfaq A. Khokhar, Michel Dubois
    Matching Algorithms and Architecture in Hierarchical Shared-Memory Multiprocessor (HMS) Systems. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:558-561 [Conf]
  35. Adrian Moga, Michel Dubois
    Performance of Asynchronous Linear Iterations with Random Delays. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:625-629 [Conf]
  36. Fong Pong, Michel Dubois
    Formal Verification of Delayed Consistency Protocols. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:124-131 [Conf]
  37. Luiz André Barroso, Michel Dubois
    The Performance of Cache-Coherent Ring-based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:268-277 [Conf]
  38. Faye A. Briggs, Michel Dubois, Kai Hwang
    Throughout Analysis and Configuration Design of a Shared-Resource Multiprocessor System: PUMPS. [Citation Graph (0, 0)][DBLP]
    ISCA, 1981, pp:67-80 [Conf]
  39. Fredrik Dahlgren, Michel Dubois, Per Stenström
    Combined Performance Gains of Simple Cache Protocol Extensions. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:187-197 [Conf]
  40. Michel Dubois, Faye A. Briggs
    Efficient Interprocessor Communications for MIMD Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1981, pp:187-196 [Conf]
  41. Michel Dubois, Faye A. Briggs
    Effects of cache coherency in multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1982, pp:299-308 [Conf]
  42. Michel Dubois, Christoph Scheurich
    Retrospective: Memory Access Buffering in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:48-50 [Conf]
  43. Michel Dubois, Christoph Scheurich, Faye A. Briggs
    Memory Access Buffering in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:434-442 [Conf]
  44. Michel Dubois, Christoph Scheurich, Faye A. Briggs
    Memory Access Buffering in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:320-328 [Conf]
  45. Michel Dubois, Jonas Skeppstedt, Livio Ricciulli, Krishnan Ramamurthy, Per Stenström
    The Detection and Elimination of Useless Misses in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:88-97 [Conf]
  46. Xiaogang Qiu, Michel Dubois
    Options for Dynamic Address Translation in COMAs. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:214-225 [Conf]
  47. Xiaogang Qiu, Michel Dubois
    Tolerating Late Memory Traps in ILP Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:76-87 [Conf]
  48. Christoph Scheurich, Michel Dubois
    Correct Memory Operation of Cache-Based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:234-243 [Conf]
  49. Jianwei Chen, Michel Dubois, Per Stenström
    Integrating complete-system and user-level performance/power simulators: the SimWattch approach. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2003, pp:1-10 [Conf]
  50. Michel Dubois, Luiz André Barroso, Yung-Syau Chen, Koray Öner
    Scalability Problems in Multiprocessors with Private Caches. [Citation Graph (0, 0)][DBLP]
    PARLE, 1992, pp:211-230 [Conf]
  51. Michel Dubois, Jin-Chin Wang, Luiz André Barroso, KangWoo Lee, Yung-Syau Chen
    Delayed consistency and its effects on the miss rate of parallel programs. [Citation Graph (0, 0)][DBLP]
    SC, 1991, pp:197-206 [Conf]
  52. Christoph Scheurich, Michel Dubois
    The design of a lockup-free cache for high-performance multiprocessors. [Citation Graph (0, 0)][DBLP]
    SC, 1988, pp:352-359 [Conf]
  53. Faye A. Briggs, Michel Dubois
    Performance of Cache-Based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1981, pp:181-190 [Conf]
  54. Jacqueline Chame, Michel Dubois
    Cache Inclusion and Processor Sampling in Multiprocessor Simulations. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1993, pp:36-47 [Conf]
  55. Christopher Ho, Heidi E. Ziegler, Michel Dubois
    In-Memory Directories: Eliminating the Cost of Directories in CC-NUMAs. [Citation Graph (0, 0)][DBLP]
    SPAA, 1998, pp:222-230 [Conf]
  56. Jaeheon Jeong, Michel Dubois
    Optimal Replacements in Caches with Two Miss Costs. [Citation Graph (0, 0)][DBLP]
    SPAA, 1999, pp:155-164 [Conf]
  57. Fong Pong, Michel Dubois
    The Verification of Cache Coherence Protocols. [Citation Graph (0, 0)][DBLP]
    SPAA, 1993, pp:11-20 [Conf]
  58. Fong Pong, Michel Dubois
    Correctness of a Directory-Based Cache Coherence Protocol: Early Experience. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:37-44 [Conf]
  59. Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Koray Öner, Michel Dubois
    RPM: A Rapid Prototyping Engine for Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1995, v:28, n:2, pp:26-34 [Journal]
  60. Michel Dubois, Shreekant S. Thakkar
    Cache Architectures in Tightly Coupled Multiprocessors - Guest Editors' Introduction to the Special Issue. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1990, v:23, n:6, pp:9-11 [Journal]
  61. Per Stenström, Mats Brorsson, Fredrik Dahlgren, Håkan Grahn, Michel Dubois
    Boosting the Performance of Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:7, pp:63-70 [Journal]
  62. Shreekant S. Thakkar, Michel Dubois, Anthony T. Laundrie, Gurindar S. Sohi, David V. James, Stein Gjessing, Manu Thapar, Bruce Delagi, Michael J. Carlton, Alvin M. Despain
    Scalable Shared-Memory Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1990, v:23, n:6, pp:71-83 [Journal]
  63. Adrian Moga, Michel Dubois
    Scalability implications of software-implemented coherence. [Citation Graph (0, 0)][DBLP]
    Comput. Syst. Sci. Eng., 2003, v:18, n:1, pp:7-15 [Journal]
  64. Jin-Chin Wang, Michel Dubois
    Performance comparison of cache coherence protocols based on the access burst model. [Citation Graph (0, 0)][DBLP]
    Comput. Syst. Sci. Eng., 1990, v:5, n:3, pp:147-158 [Journal]
  65. Fong Pong, Michel Dubois
    Verification Techniques for Cache Coherence Protocols. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1996, v:29, n:1, pp:82-126 [Journal]
  66. Michel Dubois, Jaeheon Jeong, Yong Ho Song, Adrian Moga
    Rapid Hardware Prototyping on RPM-2. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:3, pp:112-118 [Journal]
  67. Fong Pong, Michel Dubois
    Formal Verification of Complex Coherence Protocols Using Symbolic State Models. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1998, v:45, n:4, pp:557-587 [Journal]
  68. Aydin Üresin, Michel Dubois
    Parallel Asynchronous Algorithms for Discrete Data [Citation Graph (0, 0)][DBLP]
    J. ACM, 1990, v:37, n:3, pp:588-606 [Journal]
  69. Michel Dubois, Isolde Vial
    Multimedia design: the effects of relating multimodal information. [Citation Graph (0, 0)][DBLP]
    J. Comp. Assisted Learning, 2000, v:16, n:2, pp:157-165 [Journal]
  70. Michel Dubois
    Special Issue on Memory System Architectures for Scalable Multiprocessors. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1992, v:15, n:4, pp:303-304 [Journal]
  71. Michel Dubois, Jonas Skeppstedt, Per Stenström
    Essential Misses and Data Traffic in Coherence Protocols. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:29, n:2, pp:108-125 [Journal]
  72. Christoph Scheurich, Michel Dubois
    Lockup-free Caches in High-Performance Multiprocessors. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1991, v:11, n:1, pp:25-36 [Journal]
  73. Jonas Skeppstedt, Michel Dubois
    Compiler Controlled Prefetching for Multiprocessors Using Low-Overhead Traps and Prefetch Engines. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2000, v:60, n:5, pp:585-615 [Journal]
  74. Aydin Üresin, Michel Dubois
    Effects of Asynchronism on the Convergence Rate of Iterative Algorithms. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1996, v:34, n:1, pp:66-81 [Journal]
  75. KangWoo Lee, Michel Dubois
    Empirical Models of Miss Rates. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1998, v:24, n:2, pp:205-219 [Journal]
  76. Aydin Üresin, Michel Dubois
    Sufficient conditions for the convergence of asynchronous iterations. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1989, v:10, n:1, pp:83-92 [Journal]
  77. Michel Dubois, Jaeheon Jeong, Ashwini K. Nanda
    Shared cache architectures for decision support systems. [Citation Graph (0, 0)][DBLP]
    Perform. Eval., 2002, v:49, n:1/4, pp:283-298 [Journal]
  78. Luiz André Barroso, Michel Dubois
    Performance Evaluation of the Slotted Ring Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:7, pp:878-890 [Journal]
  79. Faye A. Briggs, Michel Dubois
    Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:1, pp:48-59 [Journal]
  80. Fredrik Dahlgren, Michel Dubois, Per Stenström
    Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:10, pp:1041-1055 [Journal]
  81. Michel Dubois
    A Cache-Based Multiprocessor with High Efficiency. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:10, pp:968-972 [Journal]
  82. Michel Dubois
    Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:1, pp:58-70 [Journal]
  83. Michel Dubois, Faye A. Briggs
    Effects of Cache Coherency in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:11, pp:1083-1099 [Journal]
  84. Michel Dubois, Faye A. Briggs
    The Run-Time Efficiency of Parallel Asynchronous Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:11, pp:1260-1266 [Journal]
  85. Michel Dubois, Jin-Chin Wang
    Shared Block Contention in a Cache Coherence Protocol. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:5, pp:640-644 [Journal]
  86. Jaeheon Jeong, Michel Dubois
    Cache Replacement Algorithms with Nonuniform Miss Costs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:4, pp:353-365 [Journal]
  87. Fong Pong, Michael C. Browne, Gunes Aybay, Andreas Nowatzyk, Michel Dubois
    Design Verification of the S3.mp Cache-Coherent Shared-Memory System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:1, pp:135-140 [Journal]
  88. Xiaogang Qiu, Michel Dubois
    Tolerating Late Memory Traps in Dynamically Scheduled Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:6, pp:732-743 [Journal]
  89. Christoph Scheurich, Michel Dubois
    Dynamic Page Migration in Multiprocessors with Distributed Global Memory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:8, pp:1154-1163 [Journal]
  90. Fredrik Dahlgren, Michel Dubois, Per Stenström
    Sequential Hardware Prefetching in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:7, pp:733-746 [Journal]
  91. Fong Pong, Michel Dubois
    Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2000, v:11, n:9, pp:989-1006 [Journal]
  92. Fong Pong, Michel Dubois
    A New Approach for the Verification of Cache Coherence Protocols. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:8, pp:773-787 [Journal]
  93. Xiaogang Qiu, Michel Dubois
    Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:7, pp:612-623 [Journal]
  94. Michel Dubois, Christoph Scheurich
    Memory Access Dependencies in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1990, v:16, n:6, pp:660-673 [Journal]
  95. Mafijul Md. Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois, Per Stenström
    Loop-level Speculative Parallelism in Embedded Applications. [Citation Graph (0, 0)][DBLP]
    ICPP, 2007, pp:3- [Conf]
  96. Michel Dubois, Hyunyoung Lee, Lan Lin
    STAMP: A Universal Algorithmic Model for Next-Generation Multithreaded Machines and Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  97. Jianwei Chen, Michel Dubois, Per Stenström
    SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:4, pp:34-48 [Journal]

  98. Flexible Environment for Supervising Simulation-Based Learning Situations. [Citation Graph (, )][DBLP]


  99. Supervising Distant Simulation-Based Practical Work: Environment and Experimentation. [Citation Graph (, )][DBLP]


  100. An approximate analytical model for asynchronous processes in multiprocessors. [Citation Graph (, )][DBLP]


  101. Exploiting Simulation Slack to Improve Parallel Simulation Speed. [Citation Graph (, )][DBLP]


  102. STAMP: A universal algorithmic model for next-generation multithreaded machines and systems. [Citation Graph (, )][DBLP]


  103. Dynamic MIPS rate stabilization in out-of-order processors. [Citation Graph (, )][DBLP]


  104. Seeing the Face and Observing the Actions: The Effects of Nonverbal Cues on Mediated Tutoring Dialogue. [Citation Graph (, )][DBLP]


  105. TELEOS : de l'analyse de l'activité professionnelle à la formalisation des connaissances pour un environnement d'apprentissage. [Citation Graph (, )][DBLP]


  106. Study of conditions of use of E-services accessible to visually disabled persons [Citation Graph (, )][DBLP]


  107. Assessment of a percutaneous iliosacral screw insertion simulator [Citation Graph (, )][DBLP]


Search in 0.489secs, Finished in 0.492secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002