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Cecilia Metra: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Cecilia Metra, T. M. Mak, Martin Omaña
    Fault secureness need for next generation high performance microprocessor design for testability structures. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:444-450 [Conf]
  2. Michele Favalli, Cecilia Metra
    Optimization of error detecting codes for the detection of crosstalk originated errors. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:290-296 [Conf]
  3. Michele Favalli, Cecilia Metra
    Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:612-619 [Conf]
  4. Michele Favalli, Cecilia Metra
    On the Design of Self-Checking Functional Units Based on Shannon Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:368-375 [Conf]
  5. Cecilia Metra, Michele Favalli, Bruno Riccò
    On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:763- [Conf]
  6. Cecilia Metra, Michele Favalli, Bruno Riccò
    Highly Testable and Compact 1-out-of-n Code Checker with Single Output. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:981-982 [Conf]
  7. Cecilia Metra, T. M. Mak, Martin Omaña
    Are Our Design for Testability Features Fault Secure? [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:714-715 [Conf]
  8. Cecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, S. Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi
    Novel Technique for Testing FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:89-0 [Conf]
  9. Cecilia Metra, Luca Schiano, Bruno Riccò, Michele Favalli
    Self-Checking Scheme for the On-Line Testing of Power Supply Noise. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:832-836 [Conf]
  10. Martin Omaña, José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
    Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:170-175 [Conf]
  11. Martin Omaña, Daniele Rossi, Cecilia Metra
    High Speed and Highly Testable Parallel Two-Rail Code Checker. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10608-10615 [Conf]
  12. Daniele Rossi, Carlo Steiner, Cecilia Metra
    Analysis of the impact of bus implemented EDCs on on-chip SSN. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:59-64 [Conf]
  13. Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak
    Can Clock Faults be Detected Through Functional Test? [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:168-173 [Conf]
  14. Sergio D'Angelo, Cecilia Metra, S. Pastore, A. Pogutz, Giacomo R. Sechi
    Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:233-240 [Conf]
  15. Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra
    Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:330-338 [Conf]
  16. Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra
    Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:155-163 [Conf]
  17. Michele Favalli, Cecilia Metra
    Low-level error recovery mechanism for self-checking sequential circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:234-242 [Conf]
  18. Yu-Yau Guo, Jien-Chung Lo, Cecilia Metra
    Fast and area-time efficient Berger code checkers. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:110-118 [Conf]
  19. Cecilia Metra, Stefano Di Francescantonio, Giuseppe Marrale
    On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:207-215 [Conf]
  20. Cecilia Metra, Stefano Di Francescantonio, Martin Omaña
    Automatic Modification of Sequential Circuits for Self-Checking Implementation. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:417-424 [Conf]
  21. Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
    Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:271-278 [Conf]
  22. Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
    A Highly Testable 1-out-of-3 CMOS Checker. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:279-286 [Conf]
  23. Cecilia Metra, Michele Favalli, Bruno Riccò
    CMOS Self Checking Circuits with Faulty Sequential Functional Block. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:133-141 [Conf]
  24. Cecilia Metra, Michele Favalli, Bruno Riccò
    Highly Testable and Compact 1-out-of-n CMOS Checkers. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:142-150 [Conf]
  25. Cecilia Metra, Michele Favalli, Bruno Riccò
    Compact and low power on-line self-testing voting scheme. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:137-147 [Conf]
  26. Cecilia Metra, Michele Favalli, Bruno Riccò
    Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:174-182 [Conf]
  27. Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak
    Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:357-365 [Conf]
  28. Cecilia Metra, T. M. Mak, Daniele Rossi
    Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:63-70 [Conf]
  29. Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
    The Other Side of the Timing Equation: a Result of Clock Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:169-177 [Conf]
  30. Martin Omaña, Daniele Rossi, Cecilia Metra
    Fast and Low-Cost Clock Deskew Buffer. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:202-210 [Conf]
  31. Daniele Rossi, S. Cavallotti, Cecilia Metra
    Error Correcting Codes for Crosstalk Effect Minimization. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:257-0 [Conf]
  32. Daniele Rossi, Martin Omaña, Fabio Toma, Cecilia Metra
    Multiple Transient Faults in Logic: An Issue for Next Generation ICs. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:352-360 [Conf]
  33. Xiaojun Ma, Jing Huang, Cecilia Metra, Fabrizio Lombardi
    Testing Reversible 1D Arrays for Molecular QCA. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:71-79 [Conf]
  34. Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra
    Novel Fault-Tolerant Adder Design for FPGA-Based Systems. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:54-0 [Conf]
  35. José Manuel Cazeaux, Martin Omaña, Cecilia Metra
    Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:17-24 [Conf]
  36. José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
    New High Speed CMOS Self-Checking Voter. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:58-66 [Conf]
  37. Michele Favalli, Cecilia Metra
    Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:100-105 [Conf]
  38. Cecilia Metra, A. Ferrari, Martin Omaña, Andrea Pagni
    Hardware Reconfiguration Scheme for High Availability Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:161-166 [Conf]
  39. Martin Omaña, Giacinto Papasso, Daniele Rossi, Cecilia Metra
    A Model for Transient Fault Propagation in Combinatorial Logic. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:111-0 [Conf]
  40. Daniele Rossi, V. E. S. van Dijk, Richard P. Kleihorst, A. H. Nieuwland, Cecilia Metra
    Coding Scheme for Low Energy Consumption Fault-Tolerant Bus. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:8-12 [Conf]
  41. Daniele Rossi, V. E. S. van Dijk, Richard P. Kleihorst, André K. Nieuwland, Cecilia Metra
    Power Consumption of Fault Tolerant Codes: the Active Elements. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:61-67 [Conf]
  42. Daniele Rossi, A. Muccio, André K. Nieuwland, Atul Katoch, Cecilia Metra
    Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:135-140 [Conf]
  43. Daniele Rossi, Cecilia Metra, Bruno Riccò
    Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:221-225 [Conf]
  44. Luca Schiano, Cecilia Metra, Diego Marino
    Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:243-0 [Conf]
  45. L. Di Silvio, Daniele Rossi, Cecilia Metra
    Crosstalk Effect Minimization for Encoded Busses. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:214-218 [Conf]
  46. André K. Nieuwland, Atul Katoch, Daniele Rossi, Cecilia Metra
    Coding Techniques for Low Switching Noise in Fault Tolerant Busses. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:183-189 [Conf]
  47. Martin Omaña, O. Losco, Cecilia Metra, Andrea Pagni
    On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:163-168 [Conf]
  48. José Manuel Cazeaux, Daniele Rossi, Martin Omaña, Cecilia Metra, Abhijit Chatterjee
    On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:23-28 [Conf]
  49. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra
    Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:35-40 [Conf]
  50. Daniele Rossi, Martin Omaña, Cecilia Metra, Andrea Pagni
    Checker No-Harm Alarm Robustness. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:275-280 [Conf]
  51. Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
    Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:17-22 [Conf]
  52. Cecilia Metra, Stefano Di Francescantonio, T. M. Mak
    Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:100-109 [Conf]
  53. Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
    CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:948-957 [Conf]
  54. Cecilia Metra, Michele Favalli, Bruno Riccò
    On-Line Testing Scheme for Clock's Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:587-596 [Conf]
  55. Cecilia Metra, Michele Favalli, Bruno Riccò
    On-line detection of logic errors due to crosstalk, delay, and transient faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:524-533 [Conf]
  56. Cecilia Metra, Flavio Giovanelli, Mani Soma, Bruno Riccò
    Self-checking scheme for very fast clocks' skew correction. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:652-661 [Conf]
  57. Cecilia Metra, T. M. Mak, Martin Omaña
    Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1223-1231 [Conf]
  58. Cecilia Metra, Andrea Pagano, Bruno Riccò
    On-line testing of transient and crosstalk faults affecting interconnections of FPGA-implemented systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:939-947 [Conf]
  59. Martin Omaña, Daniele Rossi, Cecilia Metra
    Novel Transient Fault Hardened Static Latch. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:886-892 [Conf]
  60. Daniele Rossi, Cecilia Metra, Bruno Riccò
    Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:27-31 [Conf]
  61. Luca Schiano, Cecilia Metra, Diego Marino
    Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:49-56 [Conf]
  62. Cecilia Metra, Michele Favalli, Bruno Riccò
    Embedded two-rail checkers with on-line testing ability. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:145-150 [Conf]
  63. Cecilia Metra, Michele Favalli, Bruno Riccò
    Highly testable and compact single output comparator. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:210-215 [Conf]
  64. Martin Omaña, Daniele Rossi, Cecilia Metra
    Low Cost Scheme for On-Line Clock Skew Compensation. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:90-95 [Conf]
  65. Cecilia Metra, Martin Omaña, T. M. Mak, S. Tam
    Novel Approach to Clock Fault Testing for High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:441-446 [Conf]
  66. Michele Favalli, Cecilia Metra
    Online Testing Approach for Very Deep-Submicron ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:2, pp:16-23 [Journal]
  67. André Ivanov, Fabrizio Lombardi, Cecilia Metra
    Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:4, pp:274-276 [Journal]
  68. Fabrizio Lombardi, Cecilia Metra
    Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:1, pp:8-9 [Journal]
  69. Cecilia Metra, Michele Favalli, Bruno Riccò
    Concurrent Checking of Clock Signal Correctness. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:4, pp:42-48 [Journal]
  70. Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra
    Exploiting ECC Redundancy to Minimize Crosstalk Impact. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:1, pp:59-70 [Journal]
  71. Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra
    New ECC for Crosstalk Impact Minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:340-348 [Journal]
  72. Jien-Chung Lo, Cecilia Metra, Fabrizio Lombardi
    Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:97-98 [Journal]
  73. Cecilia Metra, Stefano Di Francescantonio, T. M. Mak
    Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:5, pp:531-546 [Journal]
  74. Cecilia Metra, Michele Favalli, Bruno Riccò
    Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:6, pp:560-574 [Journal]
  75. Martin Omaña, Daniele Rossi, Cecilia Metra
    Low Cost and High Speed Embedded Two-Rail Code Checker. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:2, pp:153-164 [Journal]
  76. Cecilia Metra, Daniele Rossi, T. M. Mak
    Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:3, pp:415-428 [Journal]
  77. Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
    On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:770-776 [Journal]
  78. Michele Favalli, Cecilia Metra
    Interactive presentation: Pulse propagation for the detection of small delay defects. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1295-1300 [Conf]
  79. Daniele Rossi, Paolo Angelini, Cecilia Metra
    Configurable Error Control Scheme for NoC Signal Integrity. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:43-48 [Conf]
  80. Martin Omaña, Daniele Rossi, Cecilia Metra
    Latch Susceptibility to Transient Faults and New Hardening Approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:9, pp:1255-1268 [Journal]
  81. Michele Favalli, Cecilia Metra
    TMR voting in the presence of crosstalk faults at the voter inputs. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2004, v:53, n:3, pp:342-348 [Journal]
  82. Cecilia Metra, Luca Schiano, Michele Favalli
    Concurrent detection of power supply noise. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:469-475 [Journal]
  83. Michele Favalli, Cecilia Metra
    Sensing circuit for on-line detection of delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:130-133 [Journal]
  84. Michele Favalli, Cecilia Metra
    Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:392-396 [Journal]
  85. Cecilia Metra, Stefano Di Francescantonio, Michele Favalli, Bruno Riccò
    Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:1, pp:23-29 [Journal]
  86. José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
    Self-Checking Voter for High Speed TMR Systems. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:4, pp:377-389 [Journal]

  87. Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. [Citation Graph (, )][DBLP]


  88. Novel low-cost aging sensor. [Citation Graph (, )][DBLP]


  89. Testing scheme for IC's clocks. [Citation Graph (, )][DBLP]


  90. Testing Reversible One-Dimensional QCA Arrays for Multiple Faults. [Citation Graph (, )][DBLP]


  91. Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors. [Citation Graph (, )][DBLP]


  92. Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. [Citation Graph (, )][DBLP]


  93. Novel High Speed Robust Latch. [Citation Graph (, )][DBLP]


  94. Guest Editors' Introduction: The State of the Art in Nanoscale CAD. [Citation Graph (, )][DBLP]


  95. Simultaneous Switching Noise: The Relation between Bus Layout and Coding. [Citation Graph (, )][DBLP]


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