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Martin Omaña :
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Cecilia Metra , T. M. Mak , Martin Omaña Fault secureness need for next generation high performance microprocessor design for testability structures. [Citation Graph (0, 0)][DBLP ] Conf. Computing Frontiers, 2004, pp:444-450 [Conf ] Cecilia Metra , T. M. Mak , Martin Omaña Are Our Design for Testability Features Fault Secure? [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:714-715 [Conf ] Martin Omaña , José Manuel Cazeaux , Daniele Rossi , Cecilia Metra Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:170-175 [Conf ] Martin Omaña , Daniele Rossi , Cecilia Metra High Speed and Highly Testable Parallel Two-Rail Code Checker. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:10608-10615 [Conf ] Cecilia Metra , Daniele Rossi , Martin Omaña , José Manuel Cazeaux , T. M. Mak Can Clock Faults be Detected Through Functional Test? [Citation Graph (0, 0)][DBLP ] DDECS, 2006, pp:168-173 [Conf ] Cecilia Metra , Stefano Di Francescantonio , Martin Omaña Automatic Modification of Sequential Circuits for Self-Checking Implementation. [Citation Graph (0, 0)][DBLP ] DFT, 2003, pp:417-424 [Conf ] Cecilia Metra , Martin Omaña , Daniele Rossi , José Manuel Cazeaux , T. M. Mak The Other Side of the Timing Equation: a Result of Clock Faults. [Citation Graph (0, 0)][DBLP ] DFT, 2005, pp:169-177 [Conf ] Martin Omaña , Daniele Rossi , Cecilia Metra Fast and Low-Cost Clock Deskew Buffer. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:202-210 [Conf ] Daniele Rossi , Martin Omaña , Fabio Toma , Cecilia Metra Multiple Transient Faults in Logic: An Issue for Next Generation ICs. [Citation Graph (0, 0)][DBLP ] DFT, 2005, pp:352-360 [Conf ] José Manuel Cazeaux , Martin Omaña , Cecilia Metra Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop. [Citation Graph (0, 0)][DBLP ] IOLTS, 2004, pp:17-24 [Conf ] Cecilia Metra , A. Ferrari , Martin Omaña , Andrea Pagni Hardware Reconfiguration Scheme for High Availability Systems. [Citation Graph (0, 0)][DBLP ] IOLTS, 2004, pp:161-166 [Conf ] Martin Omaña , Giacinto Papasso , Daniele Rossi , Cecilia Metra A Model for Transient Fault Propagation in Combinatorial Logic. [Citation Graph (0, 0)][DBLP ] IOLTS, 2003, pp:111-0 [Conf ] Martin Omaña , O. Losco , Cecilia Metra , Andrea Pagni On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization. [Citation Graph (0, 0)][DBLP ] IOLTS, 2005, pp:163-168 [Conf ] José Manuel Cazeaux , Daniele Rossi , Martin Omaña , Cecilia Metra , Abhijit Chatterjee On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. [Citation Graph (0, 0)][DBLP ] IOLTS, 2005, pp:23-28 [Conf ] Daniele Rossi , Martin Omaña , Cecilia Metra , Andrea Pagni Checker No-Harm Alarm Robustness. [Citation Graph (0, 0)][DBLP ] IOLTS, 2006, pp:275-280 [Conf ] Cecilia Metra , Martin Omaña , Daniele Rossi , José Manuel Cazeaux , T. M. Mak Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. [Citation Graph (0, 0)][DBLP ] IOLTS, 2006, pp:17-22 [Conf ] Cecilia Metra , T. M. Mak , Martin Omaña Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. [Citation Graph (0, 0)][DBLP ] ITC, 2004, pp:1223-1231 [Conf ] Martin Omaña , Daniele Rossi , Cecilia Metra Novel Transient Fault Hardened Static Latch. [Citation Graph (0, 0)][DBLP ] ITC, 2003, pp:886-892 [Conf ] Martin Omaña , Daniele Rossi , Cecilia Metra Low Cost Scheme for On-Line Clock Skew Compensation. [Citation Graph (0, 0)][DBLP ] VTS, 2005, pp:90-95 [Conf ] Cecilia Metra , Martin Omaña , T. M. Mak , S. Tam Novel Approach to Clock Fault Testing for High Performance Microprocessors. [Citation Graph (0, 0)][DBLP ] VTS, 2007, pp:441-446 [Conf ] Martin Omaña , Daniele Rossi , Cecilia Metra Low Cost and High Speed Embedded Two-Rail Code Checker. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2005, v:54, n:2, pp:153-164 [Journal ] Martin Omaña , Daniele Rossi , Cecilia Metra Latch Susceptibility to Transient Faults and New Hardening Approach. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2007, v:56, n:9, pp:1255-1268 [Journal ] Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. [Citation Graph (, )][DBLP ] Novel low-cost aging sensor. [Citation Graph (, )][DBLP ] Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors. [Citation Graph (, )][DBLP ] Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. [Citation Graph (, )][DBLP ] Novel High Speed Robust Latch. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.303secs