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Amirali Baniasadi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Amirali Baniasadi
    Balancing clustering-induced stalls to improve performance in clustered processors. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:21-27 [Conf]
  2. Kaveh Aasaraai, Amirali Baniasadi, Ehsan Atoofian
    Computational and storage power optimizations for the O-GEHL branch predictor. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:105-112 [Conf]
  3. Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai
    Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:259-266 [Conf]
  4. Amirali Baniasadi
    Back-End Dynamic Resource Allocation Heuristics for Power-Aware High-Performance Clustered Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:240-247 [Conf]
  5. Amirali Baniasadi, Andreas Moshovos
    Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:458-461 [Conf]
  6. Andreas Moshovos, Dionisios N. Pnevmatikatos, Amirali Baniasadi
    Slice-processors: an implementation of operation-based prediction. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:321-334 [Conf]
  7. Ehsan Atoofian, Amirali Baniasadi
    Improving Energy-Efficiency by Bypassing Trivial Computations. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  8. Amirali Baniasadi, Andreas Moshovos
    Instruction flow-based front-end throttling for power-aware high-performance processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:16-21 [Conf]
  9. Amirali Baniasadi, Andreas Moshovos
    Asymmetric-frequency clustering: a power-aware back-end for high-performance processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:255-258 [Conf]
  10. Amirali Baniasadi, Andreas Moshovos
    SEPAS: a highly accurate energy-efficient branch predictor. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:38-43 [Conf]
  11. Amirali Baniasadi, Andreas Moshovos
    Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:337-347 [Conf]
  12. Amirali Baniasadi
    Power-Aware Branch Predictor Update for High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:420-429 [Conf]
  13. Babak Salamat, Amirali Baniasadi
    Area-Aware Pipeline Gating for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:601-608 [Conf]
  14. Kaveh Jokar Deris, Amirali Baniasadi
    Branchless cycle prediction for embedded processors. [Citation Graph (0, 0)][DBLP]
    SAC, 2006, pp:928-932 [Conf]
  15. Houman Homayoun, Amirali Baniasadi
    Reducing Execution Unit Leakage Power in Embedded Processors. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:299-308 [Conf]
  16. Kaveh Aasaraai, Amirali Baniasadi
    A Power-Aware Alternative for the Perceptron Branch Predictor. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:198-208 [Conf]
  17. Daniel C. Vanderster, Amirali Baniasadi, Nikitas J. Dimopoulos
    Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:175-185 [Conf]
  18. Ehsan Atoofian, Amirali Baniasadi
    A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  19. Babak Salamat, Amirali Baniasadi, Kaveh Jokar Deris
    Area-Aware Optimizations for Resource Contrained Branch Predictors Exploited in Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:50-55 [Conf]
  20. Ehsan Atoofian, Amirali Baniasadi
    Speculative trivialization point advancing in high-performance processors. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:9, pp:587-601 [Journal]
  21. Kaveh Aasaraai, Amirali Baniasadi
    Low-Power Perceptron Branch Predictor. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:333-341 [Journal]
  22. Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai
    Exploiting Speculation Cost Prediction in Power-Aware Applications. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:43-53 [Journal]

  23. Application Specific Transistor Sizing for Low Power Full Adders. [Citation Graph (, )][DBLP]


  24. Adaptive Read Validation in Time-Based Software Transactional Memory. [Citation Graph (, )][DBLP]


  25. Write Invalidation Analysis in Chip Multiprocessors. [Citation Graph (, )][DBLP]


  26. Exploiting program cyclic behavior to reduce memory latency in embedded processors. [Citation Graph (, )][DBLP]


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