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Sorin Dan Cotofana: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven
    Static cache partitioning robustness analysis for embedded on-chip multi-processors. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2006, pp:353-360 [Conf]
  2. Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven
    Compositional Memory Systems for Multimedia Communicating Tasks. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:932-937 [Conf]
  3. Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven
    Compositional, efficient caches for a chip multi-processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:345-350 [Conf]
  4. Peter Celinski, Derek Abbott, Sorin Dan Cotofana
    Area efficient, high speed parallel counter circuits using charge recycling threshold logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:233-236 [Conf]
  5. Chaohong Hu, Sorin Dan Cotofana, Jiang Jianfei
    Analysis of analog to digital converter based on single-electron tunnelling transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:693-696 [Conf]
  6. Sorin Dan Cotofana, Casper Lageweg, Stamatis Vassiliadis
    Addition Related Arithmetic Operations via Controlled Transport of Charge. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:3, pp:243-256 [Journal]
  7. Chaohong Hu, Sorin Dan Cotofana, Jianfei Jiang, Qiyu Cai
    Analog-to-digital converter based on single-electron tunneling transistors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1209-1213 [Journal]
  8. Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
    Pel reconstruction on FPGA-augmented TriMedia. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:622-635 [Journal]
  9. Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven
    Throughput optimization via cache partitioning for embedded multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:185-192 [Conf]
  10. Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven
    Compositional Memory Systems for Multimedia Communicating Tasks [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  11. Compositional, dynamic cache management for embedded chip multiprocessors. [Citation Graph (, )][DBLP]


  12. Bitstream compression techniques for Virtex 4 FPGAs. [Citation Graph (, )][DBLP]


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