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Tudor Murgan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner
    Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:404-418 [Conf]
  2. Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan
    Reconfigurable platforms for ubiquitous computing. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:377-389 [Conf]
  3. Oliver Soffke, Peter Zipf, Tudor Murgan, Manfred Glesner
    A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:632-637 [Conf]
  4. Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek
    Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1111-1114 [Conf]
  5. Mihail Petrov, Tudor Murgan, F. May, Martin Vorbach, Peter Zipf, Manfred Glesner
    The XPP Architecture and Its Co-simulation Within the Simulink Environment. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:761-770 [Conf]
  6. Alberto García Ortiz, Lukusa D. Kabulepa, Tudor Murgan, Manfred Glesner
    Moment-Based Power Estimation in Very Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:107-112 [Conf]
  7. Tudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner
    A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:323-328 [Conf]
  8. Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner
    A linear model for high-level delay estimation in VDSM on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1078-1081 [Conf]
  9. Mihail Petrov, Tudor Murgan, Abdulfattah Mohammad Obeid, Cristian Chitu, Peter Zipf, Jörg Brakensiek, Manfred Glesner
    Dynamic power optimization of the trace-back process for the Viterbi algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:721-724 [Conf]
  10. Tudor Murgan, P. B. Bacinschi, Alberto García Ortiz, Manfred Glesner
    Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:169-180 [Conf]
  11. Tudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner
    On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:819-828 [Conf]
  12. Alberto García Ortiz, Tudor Murgan, Manfred Glesner
    Moment-Based Estimation of Switching Activity for Correlated Distributions. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:859-868 [Conf]
  13. Tudor Murgan, Abdulfattah Mohammad Obeid, Andre Guntoro, Peter Zipf, Manfred Glesner, Ulrich Heinkel
    Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:151-156 [Conf]
  14. Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Manfred Glesner
    Power Estimation Based on Transition Activity Analysis with an Architecture Precise Rapid Prototyping System. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:138-0 [Conf]
  15. Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Juan Jesus, Ocampo Hidalgo, Manfred Glesner
    Emulation of Analog Components for the Rapid Prototyping of Wireless Baseband Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:172-178 [Conf]
  16. Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf
    Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:12-21 [Conf]
  17. Tudor Murgan, Clemens Schlachta, Mihail Petrov, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
    Accurate capture of timing parameters in inductively-coupled on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:117-122 [Conf]
  18. Mihail Petrov, Abdulfattah Mohammad Obeid, Tudor Murgan, Peter Zipf, Jörg Brakensiek, Bernard Ölkrug, Manfred Glesner
    An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:167-0 [Conf]
  19. Alberto García Ortiz, Tudor Murgan, Manfred Glesner
    Transition Activity Estimation for General Correlated Data Distributions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:440-445 [Conf]
  20. Tudor Murgan, P. B. Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner
    On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:242-254 [Conf]
  21. Heiko Hinkelmann, Tudor Murgan, G. Liu, Peter Zipf, Manfred Glesner
    On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:185-191 [Conf]
  22. Tudor Murgan, Andre Guntoro, Heiko Hinkelmann, P. B. Bacinschi, Manfred Glesner
    Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:7-14 [Conf]
  23. Tudor Murgan, O. Mitrea, Sujan Pandey, P. B. Bacinschi, Manfred Glesner
    Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:302-307 [Conf]
  24. Sujan Pandey, Tudor Murgan, Manfred Glesner
    Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:296-301 [Conf]

  25. An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs. [Citation Graph (, )][DBLP]


  26. Functional modeling techniques for a wireless LAN OFDM transceiver. [Citation Graph (, )][DBLP]


  27. Process variations aware robust on-chip bus architecture synthesis for MPSoCs. [Citation Graph (, )][DBLP]


  28. PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels. [Citation Graph (, )][DBLP]


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