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Ulrich Heinkel:
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Publications of Author
- Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner
Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. [Citation Graph (0, 0)][DBLP] Conf. Computing Frontiers, 2004, pp:404-418 [Conf]
- Vasco Jerinic, Jan Langer, Ulrich Heinkel, Dietmar Müller
New methods and coverage metrics for functional verification. [Citation Graph (0, 0)][DBLP] DATE, 2006, pp:1025-1030 [Conf]
- Grygoriy Bunin, Axel Schneider, Christian Haubelt, Jan Langer, Ulrich Heinkel
Automatic Test Case Generation with NuSMV. [Citation Graph (0, 0)][DBLP] GI Jahrestagung (2), 2006, pp:262-263 [Conf]
- Werner Haas, Stefan Gossens, Ulrich Heinkel
Integration of Formal Specification into the Standard ASIC Design Flow. [Citation Graph (0, 0)][DBLP] HASE, 2002, pp:189-194 [Conf]
- Axel Schneider, Stephan Walter, Jan Langer, Ulrich Heinkel
Automatic Visualization of Abstract System Specifications. [Citation Graph (0, 0)][DBLP] QSIC, 2006, pp:167-174 [Conf]
- Tudor Murgan, Abdulfattah Mohammad Obeid, Andre Guntoro, Peter Zipf, Manfred Glesner, Ulrich Heinkel
Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks. [Citation Graph (0, 0)][DBLP] ReCoSoC, 2005, pp:151-156 [Conf]
- Ulrich Heinkel, Claus Mayer, Charles F. Webb, Hans Sahm, Werner Haas, Stefan Gossens
An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs. [Citation Graph (0, 0)][DBLP] SAMOS, 2004, pp:98-107 [Conf]
- Axel Schneider, Thomas Bluhm, Tobias Renner, Ulrich Heinkel, Joachim Knablein, Reynaldo Zavala
Formal Verification of Abstract System and Protocol Specifications. [Citation Graph (0, 0)][DBLP] SEW, 2006, pp:207-211 [Conf]
Demonstration of an in-band reconfiguration data distribution and network node reconfiguration. [Citation Graph (, )][DBLP]
SpecScribe Analog - A Specification Tool Extension for Heterogeneous Systems. [Citation Graph (, )][DBLP]
A Platform for Requirement Based Formal Specification. [Citation Graph (, )][DBLP]
Formal Specification of a 40GBit/s Sonet/SDH ASIC. [Citation Graph (, )][DBLP]
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