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Salvador Petit: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Salvador Petit, Julio Sahuquillo, Jose M. Such, David R. Kaeli
    Exploiting temporal locality in drowsy cache policies. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:371-377 [Conf]
  2. Salvador Petit, Julio Sahuquillo, Ana Pont
    Characterizing Parallel Workloads to Reduce Multiple Writer Overhead in Shared Virtual Memory Systems. [Citation Graph (0, 0)][DBLP]
    PDP, 2002, pp:261-268 [Conf]
  3. Salvador Petit, Julio Sahuquillo, Ana Pont
    A Comparison Study of the HLRC-DU Protocol versus a HLRC Hardware Assisted Protocol. [Citation Graph (0, 0)][DBLP]
    PDP, 2005, pp:197-204 [Conf]
  4. Salvador Petit, Julio Sahuquillo, Ana Pont, David R. Kaeli
    Characterizing the Dynamic Behavior of Workload Execution in SVM systems. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2004, pp:230-237 [Conf]
  5. Julio Sahuquillo, Salvador Petit, Ana Pont, Veljko M. Milutinovic
    Exploring the performance of split data cache schemes on superscalar processors and symmetric multiprocessors. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2005, v:51, n:8, pp:451-469 [Journal]
  6. Salvador Petit, Julio Sahuquillo, Ana Pont, David R. Kaeli
    Addressing a workload characterization study to the design of consistency protocols. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2006, v:38, n:1, pp:49-72 [Journal]

  7. VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors. [Citation Graph (, )][DBLP]


  8. An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions. [Citation Graph (, )][DBLP]


  9. Reducing the Number of Bits in the BTB to Attack the Branch Predictor Hot-Spot. [Citation Graph (, )][DBLP]


  10. Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors. [Citation Graph (, )][DBLP]


  11. A Scheduling Heuristic to Handle Local and Remote Memory in Cluster Computers. [Citation Graph (, )][DBLP]


  12. Extending a Multicore Multithread Simulator to Model Power-Aware Hard Real-Time Systems. [Citation Graph (, )][DBLP]


  13. Dynamic task set partitioning based on balancing memory requirements to reduce power consumption. [Citation Graph (, )][DBLP]


  14. The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures. [Citation Graph (, )][DBLP]


  15. A simple power-aware scheduling for multicore systems when running real-time applications. [Citation Graph (, )][DBLP]


  16. An hybrid eDRAM/SRAM macrocell to implement first-level data caches. [Citation Graph (, )][DBLP]


  17. Balancing Task Resource Requirements in Embedded Multithreaded Multicore Processors to Reduce Power Consumption. [Citation Graph (, )][DBLP]


  18. Dynamic task set partitioning based on balancing resource requirements and utilization to reduce power consumption. [Citation Graph (, )][DBLP]


  19. Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. [Citation Graph (, )][DBLP]


  20. Applying the zeros switch-off technique to reduce static energy in data caches. [Citation Graph (, )][DBLP]


  21. An execution-driven simulation tool for teaching cache memories in introductory computer organization courses. [Citation Graph (, )][DBLP]


  22. Leakage Current Reduction in Data Caches on Embedded Systems. [Citation Graph (, )][DBLP]


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