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Adrián Cristal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero
    A first glance at Kilo-instruction based multiprocessors. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:212-221 [Conf]
  2. Adrián Cristal, Oliverio J. Santana, Mateo Valero
    Maintaining Thousands of In-flight Instructions. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:9-20 [Conf]
  3. Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
    Out-of-Order Commit Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:48-59 [Conf]
  4. Marco A. Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa
    A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:647-653 [Conf]
  5. Rubén González, Adrián Cristal, Miquel Pericàs, Mateo Valero, Alexander V. Veidenbaum
    An asymmetric clustered processor based on value content. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:61-70 [Conf]
  6. Rubén González, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero
    A Content Aware Integer Register File Organization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:314-324 [Conf]
  7. Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
    Kilo-instruction Processors. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:10-25 [Conf]
  8. Marco A. Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero
    A Simple Low-Energy Instruction Wakeup Mechanism. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:99-112 [Conf]
  9. Miquel Pericàs, Rubén González, Adrián Cristal, Alexander V. Veidenbaum, Mateo Valero
    An Optimized Front-End Physical Register File with Banking and Writeback Filtering. [Citation Graph (0, 0)][DBLP]
    PACS, 2004, pp:1-14 [Conf]
  10. Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero
    Evaluating kilo-instruction multiprocessors. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:72-79 [Conf]
  11. Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero
    A Case for Resource-conscious Out-of-order Processors. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2003, v:2, n:, pp:- [Journal]
  12. Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero
    Kilo-Instruction Processors: Overcoming the Memory Wall. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:3, pp:48-57 [Journal]
  13. Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero
    A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:3-10 [Journal]
  14. Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez
    Toward kilo-instruction processors. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:4, pp:389-417 [Journal]
  15. Marco Galluzzi, Enrique Vallejo, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero
    Implicit Transactional Memory in Kilo-Instruction Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:339-353 [Conf]
  16. Tim Harris, Adrián Cristal, Osman S. Unsal, Eduard Ayguadé, Fabrizio Gagliardi, Burton Smith, Mateo Valero
    Transactional Memory: An Overview. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:3, pp:8-29 [Journal]

  17. A Flexible Heterogeneous Multi-Core Architecture. [Citation Graph (, )][DBLP]

  18. Dynamic filtering: multi-purpose architecture support for language runtime systems. [Citation Graph (, )][DBLP]

  19. The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. [Citation Graph (, )][DBLP]

  20. Hardware Transactional Memory with Operating System Support, HTMOS. [Citation Graph (, )][DBLP]

  21. A decoupled KILO-instruction processor. [Citation Graph (, )][DBLP]

  22. Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory. [Citation Graph (, )][DBLP]

  23. QuakeTM: parallelizing a complex sequential application using transactional memory. [Citation Graph (, )][DBLP]

  24. Clock gate on abort: Towards energy-efficient hardware Transactional Memory. [Citation Graph (, )][DBLP]

  25. Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. [Citation Graph (, )][DBLP]

  26. A Two-Level Load/Store Queue Based on Execution Locality. [Citation Graph (, )][DBLP]

  27. A distributed processor state management architecture for large-window processors. [Citation Graph (, )][DBLP]

  28. EazyHTM: eager-lazy hardware transactional memory. [Citation Graph (, )][DBLP]

  29. Debugging programs that use atomic blocks and transactional memory. [Citation Graph (, )][DBLP]

  30. Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. [Citation Graph (, )][DBLP]

  31. Atomic quake: using transactional memory in an interactive multiplayer game server. [Citation Graph (, )][DBLP]

  32. Chained In-Order/Out-of-Order DoubleCore Architecture. [Citation Graph (, )][DBLP]

  33. Transactional Memory and OpenMP. [Citation Graph (, )][DBLP]

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