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Publications of Author

1. Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan
   Reconfigurable platforms for ubiquitous computing. [Citation Graph (0, 0)][DBLP]
   Conf. Computing Frontiers, 2004, pp:377-389 [Conf]
   
2. Thomas Hollstein, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner
   HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems. [Citation Graph (0, 0)][DBLP]
   CODES, 1998, pp:29-33 [Conf]
   
3. Claus Schneider, Martin Kayss, Thomas Hollstein, Jürgen Deicke
   From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:186-190 [Conf]
   
4. André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng
   Integrated Design and Test Generation Under Internet Based Environment MOSCITO. [Citation Graph (0, 0)][DBLP]
   DSD, 2002, pp:187-195 [Conf]
   
5. Thomas Hollstein, Andreas Kirschbaum, Manfred Glesner
   A prototyping environment for fuzzy controllers. [Citation Graph (0, 0)][DBLP]
   FPL, 1997, pp:482-490 [Conf]
   
6. Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek
   Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:1111-1114 [Conf]
   
7. U. Zahm, Thomas Hollstein, Hans-Jürgen Herpel, Norbert Wehn, Manfred Glesner
   Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit. [Citation Graph (0, 0)][DBLP]
   FPL, 1995, pp:241-250 [Conf]
   
8. Thomas Hollstein, Saman K. Halgamuge, Andreas Kirschbaum, Manfred Glesner
   Rapid-Prototyping von anwendungsspezifischen Fuzzy Controllern mit Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
   Fuzzy Days, 1994, pp:8-14 [Conf]
   
9. Martin K. F. Schafer, Thomas Hollstein, Heiko Zimmer, Manfred Glesner
   Deadlock-free routing and component placement for irregular mesh-based networks-on-chip. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:238-245 [Conf]
   
10. Heiko Zimmer, Stefan Zink, Thomas Hollstein, Manfred Glesner
    Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
    
11. Jochen Mades, T. Schneider, A. Windisch, Thomas Hollstein, Jürgen Becker, Manfred Glesner
    Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design. [Citation Graph (0, 0)][DBLP]
    MSE, 2001, pp:2-3 [Conf]
    
12. Thomas Hollstein, Sujan Pandey, Manfred Glesner
    Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:85-92 [Conf]
    
13. Ralf Ludewig, Thomas Hollstein, Falko Schütz, Manfred Glesner
    Rapid Prototyping of an Integrated Testing and Debugging Unit. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2004, pp:187-192 [Conf]
    
14. Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf
    Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:12-21 [Conf]
    
15. Thomas Hollstein, Ralf Ludewig, Christoph Mager, Peter Zipf, Manfred Glesner
    A hierarchical generic approach for on-chip communication, testing and debugging of SoCs. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:44-49 [Conf]
    
16. Thomas Hollstein, Manfred Glesner
    Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms. [Citation Graph (0, 0)][DBLP]
    Computers & Electrical Engineering, 2007, v:33, n:4, pp:310-319 [Journal]
    
17. 
    Multicast Parallel Pipeline Router Architecture for Network-on-Chip. [Citation Graph (, )][DBLP]
    
    
18. 
    Flexible parallel pipeline network-on-chip based on dynamic packet identity management. [Citation Graph (, )][DBLP]