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Lukás Sekanina: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lukás Sekanina
    On dependability of FPGA-based evolvable hardware systems that utilize virtual reconfigurable circuits. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2006, pp:221-228 [Conf]
  2. Lukás Sekanina, Lukás Starecek, Zdenek Kotásek
    Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:85-86 [Conf]
  3. Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina
    FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:285-289 [Conf]
  4. Lukás Sekanina
    Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:243-246 [Conf]
  5. Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina
    Testability Estimation Based on Controllability and Observability Parameters. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:504-514 [Conf]
  6. Lukás Sekanina, Vladimír Drábek
    Theory and Applications of Evolvable Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ECBS, 2004, pp:186-194 [Conf]
  7. Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel
    Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2005, pp:51-58 [Conf]
  8. Lukás Sekanina
    Towards Evolvable IP Cores for FPGAs. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2003, pp:145-154 [Conf]
  9. Lukás Sekanina, Stepan Friedl
    On Routine Implementation of Virtual Evolvable Devices Using COMBO6. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2004, pp:63-70 [Conf]
  10. Lukás Sekanina, Richard Ruzicka
    Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2003, pp:135-144 [Conf]
  11. Lukás Sekanina, Ricardo Salem Zebulum
    Evolutionary Discovering of the Concept of the Discrete State at the Transistor Level. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2005, pp:73-78 [Conf]
  12. Lukás Sekanina, Jim Torresen
    Detection of Norwegian Speed Limit Signs. [Citation Graph (0, 0)][DBLP]
    ESM, 2002, pp:337-340 [Conf]
  13. Lukás Sekanina
    From Implementations to a General Concept of Evolvable Machines. [Citation Graph (0, 0)][DBLP]
    EuroGP, 2003, pp:424-433 [Conf]
  14. Lukás Sekanina
    Image Filter Design with Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2002, pp:255-266 [Conf]
  15. Lukás Sekanina
    Evolutionary Design Space Exploration for Median Circuits. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2004, pp:240-249 [Conf]
  16. Lukás Sekanina
    Evolutionary Design of Gate-Level Polymorphic Digital Circuits. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2005, pp:185-194 [Conf]
  17. Lukás Sekanina, Zdenek Vasícek
    On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level. [Citation Graph (0, 0)][DBLP]
    EvoWorkshops, 2006, pp:344-355 [Conf]
  18. Lukás Sekanina, Azeddien M. Sllame
    Toward Uniform Approach to Design of Evolvable Hardware Based Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:814-817 [Conf]
  19. Michal Bidlo, Lukás Sekanina
    Providing information from the environment for growing electronic circuits through polymorphic gates. [Citation Graph (0, 0)][DBLP]
    GECCO Workshops, 2005, pp:242-248 [Conf]
  20. Jan Korenek, Lukás Sekanina
    Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs. [Citation Graph (0, 0)][DBLP]
    ICES, 2005, pp:46-55 [Conf]
  21. Tomás Martínek, Lukás Sekanina
    An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA. [Citation Graph (0, 0)][DBLP]
    ICES, 2005, pp:76-85 [Conf]
  22. Lukás Sekanina
    Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 2003, pp:186-197 [Conf]
  23. Lukás Sekanina, Ricardo Salem Zebulum
    Intrinsic Evolution of Controllable Oscillators in FPTA-2. [Citation Graph (0, 0)][DBLP]
    ICES, 2005, pp:98-107 [Conf]
  24. Ricardo Salem Zebulum, Adrian Stoica, Didier Keymeulen, Lukás Sekanina, Rajeshuni Ramesham, Xin Guo
    Evolvable Hardware System at Extreme Low Temperatures. [Citation Graph (0, 0)][DBLP]
    ICES, 2005, pp:37-45 [Conf]
  25. Lukás Sekanina, Vladimír Drábek
    Relation between Fault Tolerance and Reconfiguration in Cellular Systems. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:25-30 [Conf]
  26. Jim Torresen, Jorgen W. Bakke, Lukás Sekanina
    Recognizing Speed Limit Sign Numbers by Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    PPSN, 2004, pp:682-691 [Conf]
  27. Lukás Sekanina
    Evolving Constructors for Infinitely Growing Sorting Networks and Medians. [Citation Graph (0, 0)][DBLP]
    SOFSEM, 2004, pp:314-323 [Conf]
  28. Lukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek
    Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:186-193 [Conf]
  29. Lukás Sekanina
    Evolutionary Design of Digital Circuits: Where Are Current Limits? [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:171-178 [Conf]
  30. Lukás Sekanina, Stepan Friedl
    An Evolvable Combinational Unit for FPGAs. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
  31. Lukás Sekanina, Tughrul Arslan
    Evolvable Components-From Theory to Hardware Implementations. [Citation Graph (0, 0)][DBLP]
    Genetic Programming and Evolvable Machines, 2005, v:6, n:4, pp:461-462 [Journal]
  32. Lukás Sekanina, Michal Bidlo
    Evolutionary Design of Arbitrarily Large Sorting Networks Using Development. [Citation Graph (0, 0)][DBLP]
    Genetic Programming and Evolvable Machines, 2005, v:6, n:3, pp:319-347 [Journal]
  33. Karel Slaný, Lukás Sekanina
    Fitness Landscape Analysis and Image Filter Evolution Using Functional-Level CGP. [Citation Graph (0, 0)][DBLP]
    EuroGP, 2007, pp:311-320 [Conf]
  34. Zbysek Gajda, Lukás Sekanina
    Reducing the number of transistors in digital circuits using gate-level evolutionary design. [Citation Graph (0, 0)][DBLP]
    GECCO, 2007, pp:245-252 [Conf]
  35. Lukás Sekanina
    Evolvable hardware. [Citation Graph (0, 0)][DBLP]
    GECCO (Companion), 2007, pp:3627-3644 [Conf]
  36. Richard Ruzicka, Lukás Sekanina
    Evolutionary circuit design in REPOMO - reconfigurable polymorphic module. [Citation Graph (0, 0)][DBLP]
    Computational Intelligence, 2006, pp:239-244 [Conf]
  37. Zdenek Vasícek, Lukás Sekanina
    Reducing the Area on a Chip Using a Bank of Evolved Filters. [Citation Graph (0, 0)][DBLP]
    ICES, 2007, pp:222-232 [Conf]
  38. Lukás Sekanina
    Evolution of Polymorphic Self-checking Circuits. [Citation Graph (0, 0)][DBLP]
    ICES, 2007, pp:186-197 [Conf]
  39. Lukás Sekanina
    Evolutionary functional recovery in virtual reconfigurable circuits. [Citation Graph (0, 0)][DBLP]
    JETC, 2007, v:3, n:2, pp:- [Journal]

  40. A method for design of impulse bursts noise filters optimized for FPGA implementations. [Citation Graph (, )][DBLP]


  41. Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. [Citation Graph (, )][DBLP]


  42. Novel Hardware Implementation of Adaptive Median Filters. [Citation Graph (, )][DBLP]


  43. Hardware Accelerators for Cartesian Genetic Programming. [Citation Graph (, )][DBLP]


  44. Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures. [Citation Graph (, )][DBLP]


  45. An area-efficient alternative to adaptive median filtering in FPGAs. [Citation Graph (, )][DBLP]


  46. When does Cartesian genetic programming minimize the phenotype size implicitly? [Citation Graph (, )][DBLP]


  47. On Evolutionary Synthesis of Linear Transforms in FPGA. [Citation Graph (, )][DBLP]


  48. Transistor-Level Evolution of Digital Circuits Using a Special Circuit Simulator. [Citation Graph (, )][DBLP]


  49. Physical Demonstration of Polymorphic Self-Checking Circuits. [Citation Graph (, )][DBLP]


  50. Adaptive and Evolvable Hardware and Systems: The State of the Art and the Prospectus for Future Development. [Citation Graph (, )][DBLP]


  51. Evolvable Hardware: From Applications to Implications for the Theory of Computation. [Citation Graph (, )][DBLP]


  52. Evaluation of a New Platform For Image Filter Evolution. [Citation Graph (, )][DBLP]


  53. Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming. [Citation Graph (, )][DBLP]


  54. Evolutionary design of secrecy amplification protocols for wireless sensor networks. [Citation Graph (, )][DBLP]


  55. On Some Directions in Security-Oriented Research. [Citation Graph (, )][DBLP]


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