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Erik Hagersten: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Per Stenström, Erik Hagersten, David J. Lilja, Margaret Martonosi, Madan Venugopal
    Trends in Shared Memory Multiprocessing. [Citation Graph (1, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:44-50 [Journal]
  2. Mathias Spjuth, Martin Karlsson, Erik Hagersten
    Skewed caches from a low-power perspective. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:152-160 [Conf]
  3. Erik Berg, Erik Hagersten
    SIP: Performance Tuning through Source Code Interdependence. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2002, pp:177-186 [Conf]
  4. Henrik Löf, Zoran Radovic, Erik Hagersten
    THROOM - Supporting POSIX Multithreaded Binaries on a Cluster. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2003, pp:760-769 [Conf]
  5. Håkan Zeffer, Zoran Radovic, Oskar Grenholm, Erik Hagersten
    Exploiting Spatial Store Locality Through Permission Caching in Software DSMs. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:551-560 [Conf]
  6. Erik Hagersten, Ashley Saulsbury, Anders Landin
    Simple COMA Node Implementations. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:522-533 [Conf]
  7. Erik Hagersten, Michael Koster
    WildFire: A Scalable Path for SMPs. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:172-181 [Conf]
  8. Martin Karlsson, Kevin E. Moore, Erik Hagersten, David A. Wood
    Memory System Behavior of Java-Based Middleware. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:217-228 [Conf]
  9. Zoran Radovic, Erik Hagersten
    Hierarchical Backoff Locks for Nonuniform Communication Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:241-252 [Conf]
  10. Martin Karlsson, Erik Hagersten, Kevin E. Moore, David A. Wood
    Exploring Processor Design Options for Java-Based Middleware. [Citation Graph (0, 0)][DBLP]
    ICPP, 2005, pp:59-68 [Conf]
  11. Håkan Zeffer, Zoran Radovic, Martin Karlsson, Erik Hagersten
    TMA: a trap-based memory architecture. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:259-268 [Conf]
  12. Dan Wallin, Henrik Löf, Erik Hagersten, Sverker Holmgren
    Multigrid and Gauss-Seidel smoothers revisited: parallelization on chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:145-155 [Conf]
  13. Peter S. Magnusson, Anders Landin, Erik Hagersten
    Queue Locks on Cache Coherent Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPPS, 1994, pp:165-171 [Conf]
  14. Dan Wallin, Erik Hagersten
    Miss Penalty Reduction Using Bundled Capacity Prefetching in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:12- [Conf]
  15. Dan Wallin, Erik Hagersten
    Bundling: Reducing the Overhead of Multiprocessor Prefetchers. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  16. Håkan Zeffer, Zoran Radovic, Erik Hagersten
    Exploiting locality: a flexible DSM approach. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  17. Anders Landin, Erik Hagersten, Seif Haridi
    Race-Free Interconnection Networks and Multiprocessor Consistency. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:106-115 [Conf]
  18. Erik Berg, Erik Hagersten
    StatCache: a probabilistic approach to efficient and accurate data locality analysis. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2004, pp:20-27 [Conf]
  19. Erik Hagersten
    High-Performance Computers: Yesterday, Today, and Tomorrow. [Citation Graph (0, 0)][DBLP]
    PARA, 2000, pp:18- [Conf]
  20. Erik Hagersten, Mats Grindal, Anders Landin, Ashley Saulsbury, Bengt Werner, Seif Haridi
    Simulating the Data Diffusion Machine. [Citation Graph (0, 0)][DBLP]
    PARLE, 1993, pp:24-41 [Conf]
  21. Seif Haridi, Erik Hagersten
    The Cache Coherence Protocol of the Data Diffusion Machine. [Citation Graph (0, 0)][DBLP]
    PARLE (1), 1989, pp:1-18 [Conf]
  22. Dan Wallin, Håkan Zeffer, Martin Karlsson, Erik Hagersten
    VASA: A Simulator Infrastructure with Adjustable Fidelity. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2005, pp:554-563 [Conf]
  23. Zoran Radovic, Erik Hagersten
    Removing the overhead from software-based shared memory. [Citation Graph (0, 0)][DBLP]
    SC, 2001, pp:56- [Conf]
  24. Zoran Radovic, Erik Hagersten
    Efficient synchronization for nonuniform communication architectures. [Citation Graph (0, 0)][DBLP]
    SC, 2002, pp:1-13 [Conf]
  25. Erik Berg, Erik Hagersten
    Fast data-locality profiling of native execution. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2005, pp:169-180 [Conf]
  26. Per Stenström, Erik Hagersten, David J. Lilja, Margaret Martonosi, Madan Venugopal
    Shared-memory multiprocessing: Current state and future directions. [Citation Graph (0, 0)][DBLP]
    Advances in Computers, 2000, v:53, n:, pp:2-55 [Journal]
  27. Erik Hagersten, Anders Landin, Seif Haridi
    DDM - A Cache-Only Memory Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1992, v:25, n:9, pp:44-54 [Journal]
  28. Martin Karlsson, Erik Hagersten
    Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-10 [Conf]
  29. Pavlos Petoumenos, Georgios Keramidas, Håkan Zeffer, Stefanos Kaxiras, Erik Hagersten
    Modeling Cache Sharing on Chip Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    IISWC, 2006, pp:160-171 [Conf]

  30. A statistical multiprocessor cache model. [Citation Graph (, )][DBLP]

  31. StatStack: Efficient modeling of LRU caches. [Citation Graph (, )][DBLP]

  32. A case for low-complexity MP architectures. [Citation Graph (, )][DBLP]

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