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Davide Bertozzi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, Sven Jonsson
MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis. [Citation Graph (0, 0)][DBLP]
Conf. Computing Frontiers, 2006, pp:21-28 [Conf]
Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano
Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation. [Citation Graph (0, 0)][DBLP]
CP, 2005, pp:107-121 [Conf]
Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano
Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs. [Citation Graph (0, 0)][DBLP]
CPAIOR, 2006, pp:44-58 [Conf]
Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration. [Citation Graph (0, 0)][DBLP]
DAC, 2006, pp:125-130 [Conf]
Stefano Bertozzi, Andrea Acquaviva, Davide Bertozzi, Antonio Poggiali
Supporting task migration in multi-processor systems-on-chip: a feasibility study. [Citation Graph (0, 0)][DBLP]
DATE, 2006, pp:15-20 [Conf]
Davide Bertozzi, Luca Benini, Giovanni De Micheli
Low Power Error Resilient Encoding for On-Chip Data Buses. [Citation Graph (0, 0)][DBLP]
DATE, 2002, pp:102-109 [Conf]
Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi
Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. [Citation Graph (0, 0)][DBLP]
DATE, 2003, pp:10706-10713 [Conf]
Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon
Analyzing On-Chip Communication in a MPSoC Environment. [Citation Graph (0, 0)][DBLP]
DATE, 2004, pp:752-757 [Conf]
Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Francesco Poletti, Michela Milano
Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip. [Citation Graph (0, 0)][DBLP]
DATE, 2006, pp:3-8 [Conf]
Stergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo, Davide Bertozzi, Giovanni De Micheli
ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips. [Citation Graph (0, 0)][DBLP]
DATE, 2005, pp:1188-1193 [Conf]
Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino
Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
ICCD, 2002, pp:494-499 [Conf]
Matteo Dall'Osso, Gianluca Biccari, Luca Giovannini, Davide Bertozzi, Luca Benini
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs. [Citation Graph (0, 0)][DBLP]
ICCD, 2003, pp:536-0 [Conf]
Martino Ruggiero, Andrea Acquaviva, Davide Bertozzi, Luca Benini
Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms. [Citation Graph (0, 0)][DBLP]
ICCD, 2005, pp:87-93 [Conf]
Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano
Allocation and Scheduling for MPSoCs via decomposition and no-good generation. [Citation Graph (0, 0)][DBLP]
IJCAI, 2005, pp:1517-1518 [Conf]
Davide Bertozzi, Luca Benini, Bruno Riccò
Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding. [Citation Graph (0, 0)][DBLP]
ISCAS (1), 2002, pp:93-96 [Conf]
Davide Bertozzi, Luca Benini, Bruno Riccò
Parametric timing and power macromodels for high level simulation of low-swing interconnects. [Citation Graph (0, 0)][DBLP]
ISLPED, 2002, pp:307-312 [Conf]
Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini
Fault tolerance overhead in network-on-chip flow control schemes. [Citation Graph (0, 0)][DBLP]
SBCCI, 2005, pp:224-229 [Conf]
Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino
SystemC Cosimulation and Emulation of Multiprocessor SoC Designs. [Citation Graph (0, 0)][DBLP]
IEEE Computer, 2003, v:36, n:4, pp:53-59 [Journal]
Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano, Francesco Poletti
Measuring Efficiency and Executability of Allocation and Scheduling in Multi-Processor Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
Intelligenza Artificiale, 2005, v:2, n:3, pp:13-20 [Journal]
Francesco Poletti, Antonio Poggiali, Davide Bertozzi, Luca Benini, Pol Marchal, Mirko Loghi, Massimo Poncino
Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 2007, v:56, n:5, pp:606-621 [Journal]
Davide Bertozzi, Luca Benini, Giovanni De Micheli
Error control schemes for on-chip communication links: the energy-reliability tradeoff. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:818-831 [Journal]
Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:2, pp:113-129 [Journal]
Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto
Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms. [Citation Graph (0, 0)][DBLP]
DATE, 2007, pp:660-665 [Conf]
Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions. [Citation Graph (, )][DBLP]
Variation tolerant NoC design by means of self-calibrating links. [Citation Graph (, )][DBLP]
Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style. [Citation Graph (, )][DBLP]
Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels. [Citation Graph (, )][DBLP]
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints. [Citation Graph (, )][DBLP]
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs. [Citation Graph (, )][DBLP]
Network Interface Sharing Techniques for Area Optimized NoC Architectures. [Citation Graph (, )][DBLP]
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip. [Citation Graph (, )][DBLP]
Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming. [Citation Graph (, )][DBLP]
Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies. [Citation Graph (, )][DBLP]
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture. [Citation Graph (, )][DBLP]
Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip. [Citation Graph (, )][DBLP]
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework. [Citation Graph (, )][DBLP]
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing. [Citation Graph (, )][DBLP]
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints. [Citation Graph (, )][DBLP]

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