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Tsutomu Maruyama: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tohru Moto-Oka, Hidehiko Tanaka, Hitoshi Aida, Keiji Hirata, Tsutomu Maruyama
    The Architecture of a Parallel Inference Engine - PIE. [Citation Graph (1, 0)][DBLP]
    FGCS, 1984, pp:479-488 [Conf]
  2. Youhei Hori, Minenobu Seki, Reijer Grimbergen, Tsutomu Maruyama, Tsutomu Hoshino
    A Shogi Processor with a Field Programmable Gate Array. [Citation Graph (0, 0)][DBLP]
    Computers and Games, 2000, pp:297-314 [Conf]
  3. Yoshiki Yamaguchi, Tsutomu Maruyama, Tsutomu Hoshino
    High Speed Hardware Computation of Co-evolution Models. [Citation Graph (0, 0)][DBLP]
    ECAL, 1999, pp:566-574 [Conf]
  4. Shingo Masuno, Tsutomu Maruyama, Yoshiki Yamaguchi, Akihiko Konagaya
    Multidimensional Dynamic Programming for Homology Search on Distributed Systems. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2006, pp:1127-1137 [Conf]
  5. Tsutomu Maruyama, Tsutomu Hoshino
    A C to HDL Compiler for Pipeline Processing on FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:101-112 [Conf]
  6. Koichi Konishi, Tsutomu Maruyama, Akihiko Konagaya, Kaoru Yoshida, Takashi Chikayama
    Implementing Streams on Parallel Machines with Distributed Memory. [Citation Graph (0, 0)][DBLP]
    FGCS, 1992, pp:791-798 [Conf]
  7. Toshihito Fujiwara, Kenji Fujimoto, Tsutomu Maruyama
    A Real-Time Visualization System for PIV. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:437-447 [Conf]
  8. Kenji Kanazawa, Tsutomu Maruyama
    An FPGA Solver for WSAT Algorithms. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:83-88 [Conf]
  9. Tomoyoshi Kobori, Tsutomu Maruyama
    High Speed Computation of Three Dimensional Cellular Automata with FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1126-1130 [Conf]
  10. Tomoyoshi Kobori, Tsutomu Maruyama
    A High Speed Computation System for 3D FCHC Lattice Gas Model with FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:755-765 [Conf]
  11. Tomoyoshi Kobori, Tsutomu Maruyama, Tsutomu Hoshino
    High Speed Computation of Lattice gas Automata with FPFA. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:801-804 [Conf]
  12. Tsutomu Maruyama
    Real-Time Computation of the Generalized Hough Transform. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:980-985 [Conf]
  13. Tsutomu Maruyama, Terunobu Funatsu, Tsutomu Hoshino
    A Field-Programmable Gate-Array System for Evolutionary Computation. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:356-365 [Conf]
  14. Tsutomu Maruyama, Tsutomu Hoshino
    A Reconfigurable Architecture for High Speed Computation by Pipeline Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:514-519 [Conf]
  15. Tsutomu Maruyama, Masaaki Takagi, Tsutomu Hoshino
    Hardware Implementation Techniques for Recursive Calls and Loops. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:450-455 [Conf]
  16. Tsutomu Maruyama, Yoshiki Yamaguchi, Atsushi Kawase
    An Approach to Real-Time Visualization of PIV Method with FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:601-606 [Conf]
  17. Shingo Masuno, Tsutomu Maruyama, Yoshiki Yamaguchi, Akihiko Konagaya
    Multidimensional Dynamic Programming for Homology Search. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:173-178 [Conf]
  18. Yosuke Miyajima, Tsutomu Maruyama
    A Real-Time Stereo Vision System with FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:448-457 [Conf]
  19. Akira Miyashita, Toshihito Fujiwara, Tsutomu Maruyama
    A Placement/Routing Approach for FPGA Accelerators. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1177-1182 [Conf]
  20. Hiroaki Niitsuma, Tsutomu Maruyama
    Real-Time Detection of Moving Objects. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1155-1157 [Conf]
  21. Hiroaki Niitsuma, Tsutomu Maruyama
    Real-time Generation of Three-Dimensional Motion Fields. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:179-184 [Conf]
  22. Takashi Saito, Tsutomu Maruyama, Tsutomu Hoshino, Saburo Hirano
    A Music Synthesizer on FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:377-387 [Conf]
  23. Yoshiki Yamaguchi, Tsutomu Maruyama, Akihiko Konagaya
    Three-Dimensional Dynamic Programming for Homology Search. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:505-515 [Conf]
  24. Yoshiki Yamaguchi, Akira Miyashita, Tsutomu Maruyama, Tsutomu Hoshino
    A Co-processor System with a Virtex FPGA for Evolutionary Computation. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:240-249 [Conf]
  25. Yoshiki Yamaguchi, Yosuke Miyajima, Tsutomu Maruyama, Akihiko Konagaya
    High Speed Homology Search Using Run-Time Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:281-291 [Conf]
  26. Yoshiki Yamaguchi, Tsutomu Maruyama, Ryuzo Azuma, Akihiko Konagaya
    Spatiotemporal Simulation of a Single Living Cell. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:267-274 [Conf]
  27. Tsutomu Maruyama, Tetsuya Hirose, Akihiko Konagaya
    A Fine-Grained Parallel Genetic Algorithm for Distributed Parallel Systems. [Citation Graph (0, 0)][DBLP]
    ICGA, 1993, pp:184-190 [Conf]
  28. Nozomu Nagata, Tsutomu Maruyama
    A Compact System for Real-Time Detection of Line Segments. [Citation Graph (0, 0)][DBLP]
    ICIAP, 2005, pp:220-228 [Conf]
  29. Hiroaki Niitsuma, Tsutomu Maruyama
    High Speed Computation of the Optical Flow. [Citation Graph (0, 0)][DBLP]
    ICIAP, 2005, pp:287-295 [Conf]
  30. Tsutomu Maruyama
    Real-time K-Means Clustering for Color Images on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ICPR (2), 2006, pp:816-819 [Conf]
  31. Toshiaki Tarui, Tsutomu Maruyama, Hidehiko Tanaka
    A Preliminary Evaluation of a Parallel Inference Machine for Stream Parallel Languages. [Citation Graph (0, 0)][DBLP]
    LP, 1987, pp:132-147 [Conf]
  32. Tsutomu Maruyama, Keiji Hirata, Hidehiko Tanaka, Tohru Moto-Oka
    A Note on the Elementary Execution Unit in a Parallel Inference Machine. [Citation Graph (0, 0)][DBLP]
    LP, 1985, pp:25-34 [Conf]
  33. Tsutomu Maruyama, Akihiko Konagaya, Koichi Konishi
    An Asynchronous Fine-Grained Parallel Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    PPSN, 1992, pp:569-578 [Conf]
  34. Yoshiki Yamaguchi, Tsutomu Maruyama, Akihiko Konagaya
    High Speed Homology Search with FPGAs. [Citation Graph (0, 0)][DBLP]
    Pacific Symposium on Biocomputing, 2002, pp:271-282 [Conf]
  35. Kenichi Tayama, Takashi Inoue, Tsutomu Maruyama, Hiroshi Uno
    An Operation Support System Architecture and Process for Optical Access Network Allocation during Service Provisioning. [Citation Graph (0, 0)][DBLP]
    J. Network Syst. Manage., 2004, v:12, n:3, pp:- [Journal]
  36. Takashi Saegusa, Tsutomu Maruyama
    An FPGA Implementation of K-Means Clustering for Color Images Based on Kd-Tree. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  37. Kenji Kanazawa, Tsutomu Maruyama
    An FPGA Solver for Large SAT Problems. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  38. Dang Ba Khac Trieu, Tsutomu Maruyama
    Implementation of a Parallel and Pipelined Watershed Algorithm on FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  39. Yoshiki Yamaguchi, Kenji Kanazawa, Yoshiharu Ohke, Tsutomu Maruyama
    An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemma. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:358-364 [Conf]
  40. Yoshiki Yamaguchi, Tsutomu Maruyama, Ryuzo Azuma, Moritoshi Yasunaga, Akihiko Konagaya
    Mesoscopic-level Simulation of Dynamics and Interactions of Biological Molecules Using Monte Carlo Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:48, n:3, pp:287-299 [Journal]

  41. An FPGA Solver for Very Large SAT Problems. [Citation Graph (, )][DBLP]


  42. A Pipeline Implementation of a Watershed Algorithm on FPGA. [Citation Graph (, )][DBLP]


  43. An FPGA Implementation of Multiple Sequence Alignment Based on Carrillo-Lipman Method. [Citation Graph (, )][DBLP]


  44. High speed tablation system using an FPGA designed for distribution tables of frequent DNA subsequences. [Citation Graph (, )][DBLP]


  45. How fast is an FPGA in image processing? [Citation Graph (, )][DBLP]


  46. Performance comparison of FPGA, GPU and CPU in image processing. [Citation Graph (, )][DBLP]


  47. Real-time processing of local contrast enhancement on FPGA. [Citation Graph (, )][DBLP]


  48. Accelerating HMMER search using FPGA. [Citation Graph (, )][DBLP]


  49. A Lattice Gas Cellular Automata Simulator on the Cell Broadband Engine. [Citation Graph (, )][DBLP]


  50. An operation support system architecture for network provisioning of optical access networks. [Citation Graph (, )][DBLP]


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