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Steven Wallace: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Steven Wallace, Kim M. Hazelwood
    SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:209-220 [Conf]
  2. Steven Wallace, Nader Bagherzadeh
    Instruction Fetching Mechanisms for Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. II, 1996, pp:747-756 [Conf]
  3. Steven Wallace, Nader Bagherzadeh
    Multiple Branch and Block Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:94-0 [Conf]
  4. Steven Wallace, Dean M. Tullsen, Brad Calder
    Instruction Recycling on a Multiple-Path Processor. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:44-53 [Conf]
  5. Steven Wallace, Nirav Dagli, Nader Bagherzadeh
    Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:96-101 [Conf]
  6. Steven Wallace, Nader Bagherzadeh
    Performance Issues of a Superscalar Microprocessor. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:293-297 [Conf]
  7. Steven Wallace, Brad Calder, Dean M. Tullsen
    Threaded Multiple Path Execution. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:238-249 [Conf]
  8. Chi-Keung Luk, Robert S. Cohn, Robert Muth, Harish Patil, Artur Klauser, P. Geoffrey Lowney, Steven Wallace, Vijay Janapa Reddi, Kim M. Hazelwood
    Pin: building customized program analysis tools with dynamic instrumentation. [Citation Graph (0, 0)][DBLP]
    PLDI, 2005, pp:190-200 [Conf]
  9. Joel S. Emer, Pritpal Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan
    Asim: A Performance Model Framework. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:2, pp:68-76 [Journal]
  10. Cees de Laat, Erik Radius, Steven Wallace
    The rationale of the current optical networking initiatives. [Citation Graph (0, 0)][DBLP]
    Future Generation Comp. Syst., 2003, v:19, n:6, pp:999-1008 [Journal]
  11. Steven Wallace, Nader Bagherzadeh
    Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:6, pp:570-578 [Journal]

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