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Onur Mutlu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt
    Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:367-378 [Conf]
  2. Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt
    2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set. [Citation Graph (0, 0)][DBLP]
    CGO, 2006, pp:159-172 [Conf]
  3. Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt
    Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:434-443 [Conf]
  4. Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt
    Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:129-140 [Conf]
  5. Onur Mutlu, Hyesoon Kim, Yale N. Patt
    Techniques for Efficient Processing in Runahead Execution Engines. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:370-381 [Conf]
  6. Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt
    A Case for MLP-Aware Cache Replacement. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:167-178 [Conf]
  7. David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt
    Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:119-128 [Conf]
  8. Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt
    Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:43-54 [Conf]
  9. Onur Mutlu, Hyesoon Kim, Yale N. Patt
    Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:233-244 [Conf]
  10. Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt
    Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:53-64 [Conf]
  11. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
    Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2004, pp:2-9 [Conf]
  12. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
    Understanding the effects of wrong-path memory references on processor performance. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:56-64 [Conf]
  13. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
    Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:5, pp:529-559 [Journal]
  14. Hyesoon Kim, Onur Mutlu, Yale N. Patt, Jared Stark
    Wish Branches: Enabling Adaptive and Aggressive Predicated Execution. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:48-58 [Journal]
  15. Onur Mutlu, Hyesoon Kim, Yale N. Patt
    Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:10-20 [Journal]
  16. Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt
    Runahead Execution: An Effective Alternative to Large Instruction Windows. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:20-25 [Journal]
  17. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
    An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:12, pp:1556-1571 [Journal]
  18. Onur Mutlu, Hyesoon Kim, Yale N. Patt
    Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:12, pp:1491-1508 [Journal]
  19. Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn
    VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:424-435 [Conf]
  20. Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt
    Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:94-104 [Journal]

  21. Improving the performance of object-oriented languages with dynamic predication of indirect jumps. [Citation Graph (, )][DBLP]


  22. Accelerating critical section execution with asymmetric multi-core architectures. [Citation Graph (, )][DBLP]


  23. Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. [Citation Graph (, )][DBLP]


  24. Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. [Citation Graph (, )][DBLP]


  25. Performance-aware speculation control using wrong path usefulness prediction. [Citation Graph (, )][DBLP]


  26. Express Cube Topologies for on-Chip Interconnects. [Citation Graph (, )][DBLP]


  27. Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. [Citation Graph (, )][DBLP]


  28. Operating system scheduling for efficient online self-test in robust systems. [Citation Graph (, )][DBLP]


  29. Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems. [Citation Graph (, )][DBLP]


  30. Architecting phase change memory as a scalable dram alternative. [Citation Graph (, )][DBLP]


  31. Self-Optimizing Memory Controllers: A Reinforcement Learning Approach. [Citation Graph (, )][DBLP]


  32. Flexible reference-counting-based hardware acceleration for garbage collection. [Citation Graph (, )][DBLP]


  33. A case for bufferless routing in on-chip networks. [Citation Graph (, )][DBLP]


  34. Aérgia: exploiting packet latency slack in on-chip networks. [Citation Graph (, )][DBLP]


  35. Data marshaling for multi-core architectures. [Citation Graph (, )][DBLP]


  36. Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. [Citation Graph (, )][DBLP]


  37. Coordinated control of multiple prefetchers in multi-core systems. [Citation Graph (, )][DBLP]


  38. Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. [Citation Graph (, )][DBLP]


  39. Improving memory bank-level parallelism in the presence of prefetching. [Citation Graph (, )][DBLP]


  40. Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. [Citation Graph (, )][DBLP]


  41. Prefetch-Aware DRAM Controllers. [Citation Graph (, )][DBLP]


  42. Application-aware prioritization mechanisms for on-chip networks. [Citation Graph (, )][DBLP]


  43. Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip. [Citation Graph (, )][DBLP]


  44. Distributed order scheduling and its application to multi-core dram controllers. [Citation Graph (, )][DBLP]


  45. QuaLe: A Quantum-Leap Inspired Model for Non-stationary Analysis of NoC Traffic in Chip Multi-processors. [Citation Graph (, )][DBLP]


  46. Phase change memory architecture and the quest for scalability. [Citation Graph (, )][DBLP]


  47. Dynamic Predication of Indirect Jumps. [Citation Graph (, )][DBLP]


  48. On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor. [Citation Graph (, )][DBLP]


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