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John W. O'Leary: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mark Aagaard, Thomas F. Melham, John W. O'Leary
    Xs are for Trajectory Evaluation, Booleans are for Theorem Proving. [Citation Graph (0, 0)][DBLP]
    CHARME, 1999, pp:202-218 [Conf]
  2. John W. O'Leary, Mark H. Linderman, Miriam Leeser, Mark Aagaard
    HML: A Hardware Description Language Based on Standard ML. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:327-334 [Conf]
  3. Mark Aagaard, Robert B. Jones, Thomas F. Melham, John W. O'Leary, Carl-Johan H. Seger
    A Methodology for Large-Scale Hardware Verification. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:263-282 [Conf]
  4. Yirng-An Chen, Edmund M. Clarke, Pei-Hsin Ho, Yatin Vasant Hoskote, Timothy Kam, Manpreet Khaira, John W. O'Leary, Xudong Zhao
    Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:19-33 [Conf]
  5. Miriam Leeser, John W. O'Leary
    Verification of a subtractive radix-2 square root algorithm and implementation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:526-531 [Conf]
  6. John W. O'Leary, Miriam Leeser, Jason Hickey, Mark Aagaard
    Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:52-71 [Conf]
  7. Robert B. Jones, John W. O'Leary, Carl-Johan H. Seger, Mark Aagaard, Thomas F. Melham
    Practical Formal Verification in Microprocessor Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:4, pp:16-25 [Journal]
  8. Jim Grundy, Thomas F. Melham, John W. O'Leary
    A reflective functional language for hardware design and theorem proving. [Citation Graph (0, 0)][DBLP]
    J. Funct. Program., 2006, v:16, n:2, pp:157-196 [Journal]
  9. Carl-Johan H. Seger, Robert B. Jones, John W. O'Leary, Thomas F. Melham, Mark Aagaard, Clark Barrett, Don Syme
    An industrially effective environment for formal hardware verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1381-1405 [Journal]

  10. Protocol verification using flows: An industrial experience. [Citation Graph (, )][DBLP]


  11. Verifying Correctness of Transactional Memories. [Citation Graph (, )][DBLP]


  12. Model Checking Transactional Memory with Spin. [Citation Graph (, )][DBLP]


  13. Extracting models from design documents with mapster. [Citation Graph (, )][DBLP]


  14. Model checking transactional memory with spin. [Citation Graph (, )][DBLP]


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