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George Economakos: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. George Economakos, George K. Papakonstantinou
    Refinement and Property Checking in High-Level Synthesis using Attribute Grammars. [Citation Graph (0, 0)][DBLP]
    CHARME, 1999, pp:330-333 [Conf]
  2. George Economakos, George K. Papakonstantinou, Kiamal Z. Pekmestzi, Panayotis Tsanakas
    Hardware compilation using attribute grammars. [Citation Graph (0, 0)][DBLP]
    CHARME, 1997, pp:273-290 [Conf]
  3. George Economakos, Petros Oikonomakos, Ioannis Panagopoulos, Ioannis Poulakis, George K. Papakonstantinou
    Behavioral synthesis with systemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:21-25 [Conf]
  4. George Economakos, George K. Papakonstantinou, Panayotis Tsanakas
    AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:933-934 [Conf]
  5. George Economakos, Stergios Stergiou, George K. Papakonstantinou, Vassilios Zoukos
    A Multi-Lingual Synthesis and Verification Environment. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:8-15 [Conf]
  6. George Economakos, George K. Papakonstantinou
    Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10091-10098 [Conf]
  7. George Economakos, George K. Papakonstantinou
    Language Based Design Verification with Semantic Analysis. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1268-0 [Conf]
  8. Nectarios Koziris, Theodore Andronikos, George Economakos, George K. Papakonstantinou, Panayotis Tsanakas
    Automatic Hardware Synthesis of Nested Loops Using UET Grids and VHDL. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1997, pp:888-897 [Conf]
  9. George Economakos
    High-level synthesis with reconfigurable datapath components. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  10. George Economakos, George K. Papakonstantinou, Panayotis Tsanakas
    Incorporating multi-pass attribute grammars for the high-level synthesis of ASICs. [Citation Graph (0, 0)][DBLP]
    SAC, 1998, pp:45-49 [Conf]
  11. George Economakos, Petros Oikonomakos, Ioannis Poulakis, George K. Papakonstantinou, Stamatis Georgoulis
    Handling advanced scheduling heuristics under a hardware compiler generation environment. [Citation Graph (0, 0)][DBLP]
    Knowl.-Based Syst., 2002, v:15, n:1-2, pp:3-11 [Journal]
  12. George Economakos, Christoforos Economakos, Sotirios Xydis
    Run-time reconfigurable solutions for adaptive control applications. [Citation Graph (0, 0)][DBLP]
    ICINCO-SPSMC, 2007, pp:208-213 [Conf]
  13. George Economakos
    Behavioral synthesis with SystemC and PSL assertions for interface specification. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  14. George Economakos, K. Anagnostopoulos
    Bit level architectural exploration technique for the design of low power multipliers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  15. Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi
    Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:137-144 [Conf]

  16. Efficient implementation of biomedical hardware using open source descriptions and behavioral synthesis. [Citation Graph (, )][DBLP]


  17. Construction of dual mode components for reconfiguration aware high-level synthesis. [Citation Graph (, )][DBLP]


  18. A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis. [Citation Graph (, )][DBLP]


  19. Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis. [Citation Graph (, )][DBLP]


  20. Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology. [Citation Graph (, )][DBLP]


  21. High-level synthesis with coarse grain reconfigurable components. [Citation Graph (, )][DBLP]


  22. An instruction set extension for java bytecodes translation acceleration. [Citation Graph (, )][DBLP]


  23. A Reconfigurable Arithmetic Data-path Based On Regular Interconnection. [Citation Graph (, )][DBLP]


  24. Optimized FPGA implementations of demanding PLC programs based on hardware high-level synthesis. [Citation Graph (, )][DBLP]


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