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Publications of Author

1. Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir
   Using Abstract Specifications to Verify PowerPC^TM Custom Memories by Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
   CHARME, 2001, pp:386-402 [Conf]
   
2. Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham
   Full chip false timing path identification: applications to the PowerPCTM microprocessors. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:514-519 [Conf]
   
3. Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham
   Improving Witness Search Using Orders on States. [Citation Graph (0, 0)][DBLP]
   ICCD, 1999, pp:452-457 [Conf]
   
4. Jayanta Bhadra, Narayanan Krishnamurthy
   Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
   ITC, 2002, pp:213-222 [Conf]
   
5. Alper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra
   Formal Verification of a System-on-Chip Using Computation Slicing. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:810-819 [Conf]
   
6. Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova
   Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. [Citation Graph (0, 0)][DBLP]
   MTV, 2005, pp:111-118 [Conf]
   
7. Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir
   A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. [Citation Graph (0, 0)][DBLP]
   MTV, 2003, pp:32-37 [Conf]
   
8. Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir
   Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. [Citation Graph (0, 0)][DBLP]
   MTV, 2006, pp:33-36 [Conf]
   
9. Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
   Towards The Complete Elimination of Gate/Switch Level Simulations. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2004, pp:115-0 [Conf]
   
10. Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham
    Automatic Validation Test Generation Using Extracted Control Models. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:312-0 [Conf]
    
11. Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
    Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:275-280 [Conf]
    
12. Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra
    Program Slicing for Hierarchical Test Generation. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:237-246 [Conf]
    
13. Kyoil Kim, Jacob A. Abraham, Jayanta Bhadra
    Model Checking of Security Protocols with Pre-configuration. [Citation Graph (0, 0)][DBLP]
    WISA, 2003, pp:1-15 [Conf]
    
14. Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir
    Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:494-502 [Journal]
    
15. Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham
    A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2005, v:27, n:1-2, pp:67-112 [Journal]
    
16. 
    A Mechanized Refinement Framework for Analysis of Custom Memories. [Citation Graph (, )][DBLP]
    
    
17. 
    Accelerating multi-party scheduling for transaction-level modeling. [Citation Graph (, )][DBLP]
    
    
18. 
    An incremental learning framework for estimating signal controllability in unit-level verification. [Citation Graph (, )][DBLP]
    
    
19. 
    On soft error rate analysis of scaled CMOS designs - A statistical perspective. [Citation Graph (, )][DBLP]
    
    
20. 
    An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs. [Citation Graph (, )][DBLP]
    
    
21. 
    Modeling and verification of industrial flash memories. [Citation Graph (, )][DBLP]
    
    
22. 
    A Survey of Hybrid Techniques for Functional Verification. [Citation Graph (, )][DBLP]
    
    
23. 
    Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. [Citation Graph (, )][DBLP]