The SCEAS System
Navigation Menu

Search the dblp DataBase


Amit Narayan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Subramanian K. Iyer, Debashis Sahoo, Christian Stangier, Amit Narayan, Jawahar Jain
    Improved Symbolic Verification Using Partitioning Techniques. [Citation Graph (0, 0)][DBLP]
    CHARME, 2003, pp:410-424 [Conf]
  2. Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Engineering Change in a Non-Deterministic FSM Setting. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:451-456 [Conf]
  3. J. Ramanujam, Jinpyo Hong, Mahmut T. Kandemir, Amit Narayan
    Reducing Memory Requirements of Nested Loops for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:359-364 [Conf]
  4. Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, E. Allen Emerson
    A Partitioning Methodology for BDD-Based Verification. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2004, pp:399-413 [Conf]
  5. Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita
    Decomposition Techniques for Efficient ROBDD Construction. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:419-434 [Conf]
  6. Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
    Logic synthesis for large pass transistor circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:663-670 [Conf]
  7. Eric Felt, Amit Narayan, Alberto L. Sangiovanni-Vincentelli
    Measurement and modeling of MOS transistor current mismatch in analog IC's. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:272-277 [Conf]
  8. Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Wireplanning in logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:26-33 [Conf]
  9. Amit Mehrotra, Suihua Lu, David C. Lee, Amit Narayan
    Steady-state analysis of voltage and current controlled oscillators. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:618-623 [Conf]
  10. Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Reachability analysis using partitioned-ROBDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:388-393 [Conf]
  11. Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
    Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:547-554 [Conf]
  12. Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
    A Survey of Techniques for Formal Verification of Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:445-454 [Conf]
  13. Suihua Lu, Amit Narayan, Amit Mehrotra
    Continuation method in multitone harmonic balance. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:520-523 [Conf]
  14. Makram M. Mansour, Amit Mehrotra, William W. Walker, Amit Narayan
    Analysis techniques for obtaining the steady-state solution of MOS LC oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:512-515 [Conf]
  15. J. Ramanujam, Amit Narayan
    Integrating Data Distribution and Loop Transformations. [Citation Graph (0, 0)][DBLP]
    PPSC, 1995, pp:668-673 [Conf]
  16. Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
    Formal Verification of Combinational Circuit. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:218-225 [Conf]
  17. Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    A study of composition schemes for mixed apply/compose based construction of ROBDDs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:249-253 [Conf]

Search in 0.147secs, Finished in 0.149secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002