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Title:
Author:
Massimo Poncino: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gianpiero Cabodi, Paolo Camurati, Antonio Lioy, Massimo Poncino, Stefano Quer
    A parallel approach to symbolic traversal based on set partitioning. [Citation Graph (0, 0)][DBLP]
    CHARME, 1997, pp:167-184 [Conf]
  2. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Computational Kernels and their Application to Sequential Power Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:764-769 [Conf]
  3. Luca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino
    From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:784-789 [Conf]
  4. Luca Benini, Giovanni De Micheli, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:247-252 [Conf]
  5. Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Fabrizio Pro, Massimo Poncino
    Energy-aware design techniques for differential power analysis protection. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:36-41 [Conf]
  6. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Synthesis of application-specific memories for power optimization in embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:300-303 [Conf]
  7. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:128-133 [Conf]
  8. Luca Benini, Enrico Macii, Massimo Poncino
    Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:22-27 [Conf]
  9. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto
    Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:467-470 [Conf]
  10. Franco Fummi, Giovanni Perbellini, Paolo Gallo, Massimo Poncino, Stefano Martini, Fabio Ricciato
    A timing-accurate modeling and simulation environment for networked embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:42-47 [Conf]
  11. Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino
    Computing the Maximum Power Cycles of a Sequential Circuit. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:23-28 [Conf]
  12. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    A Discrete-Time Battery Model for High-Level Power Estimation. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:35-0 [Conf]
  13. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Extending lifetime of portable systems by battery scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:197-203 [Conf]
  14. Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Glitch Power Minimization by Gate Freezing. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:163-167 [Conf]
  15. Ashutosh Chakraborty, Prassanna Sithambaram, K. Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino
    Thermal resilient bounded-skew clock tree optimization methodology. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:832-837 [Conf]
  16. Nicola Drago, Franco Fummi, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino
    Estimation of Bus Performance for a Tuplespace in an Embedded Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20188-20195 [Conf]
  17. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino
    Power Estimation of Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:762-766 [Conf]
  18. Franco Fummi, Mirko Loghi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino
    Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:798-803 [Conf]
  19. Franco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino
    Modeling and Analysis of Heterogeneous Industrial Networks Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:342-344 [Conf]
  20. Franco Fummi, Stefano Martini, Giovanni Perbellini, Massimo Poncino
    Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:564-569 [Conf]
  21. Franco Fummi, Stefano Martini, Giovanni Perbellini, Massimo Poncino, Fabio Ricciato, Maura Turolla
    Heterogeneous Co-Simulation of Networked Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:168-173 [Conf]
  22. Mirko Loghi, Paolo Azzoni, Massimo Poncino
    Tag Overflow Buffering: An Energy-Efficient Cache Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:520-525 [Conf]
  23. Mirko Loghi, Massimo Poncino
    Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:508-513 [Conf]
  24. Luca Macchiarulo, Enrico Macii, Massimo Poncino
    Wire Placement for Crosstalk Energy Minimization in Address Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:158-162 [Conf]
  25. Alberto Macii, Enrico Macii, Massimo Poncino
    Improving the Efficiency of Memory Partitioning by Address Clustering. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10018-10023 [Conf]
  26. Kimish Patel, Enrico Macii, Massimo Poncino
    Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:700-701 [Conf]
  27. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi
    A State Space Decomposition Algorithm for Approximate FSM Traversal. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:137-141 [Conf]
  28. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1311-1317 [Conf]
  29. Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino
    Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:8-12 [Conf]
  30. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Timed Supersetting and the Synthesis of Telescopic Units. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:331-337 [Conf]
  31. Alberto Bocca, Sabino Salerno, Enrico Macii, Massimo Poncino
    Energy-efficient bus encoding for LCD displays. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:240-243 [Conf]
  32. Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Massimo Poncino, Fabrizio Pro
    A novel architecture for power maskable arithmetic units. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:136-140 [Conf]
  33. Luca Benini, Alessandro Bogliolo, Enrico Macii, Massimo Poncino, Mihai Surmei
    Regression-based RTL power models for controllers. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:147-152 [Conf]
  34. Luca Benini, Marco Ferrero, Alberto Macii, Enrico Macii, Massimo Poncino
    Supporting system-level power exploration for DSP applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:17-22 [Conf]
  35. Roberto Corgnati, Enrico Macii, Massimo Poncino
    Clustered Table-Based Macromodels for RTL Power Estimation. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:354-357 [Conf]
  36. Monica Donno, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino
    Enhanced clustered voltage scaling for low power. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:18-23 [Conf]
  37. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto
    Test Generation for Networks of Interacting FSMs Using Symbolic Techniques. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:208-213 [Conf]
  38. Franco Fummi, Giovanni Perbellini, Mirko Loghi, Massimo Poncino
    ISS-centric modular HW/SW co-simulation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:31-36 [Conf]
  39. Antonio Lioy, Enrico Macii, Massimo Poncino, Massimo Rossello
    Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:70-0 [Conf]
  40. Mirko Loghi, Martin Letis, Luca Benini, Massimo Poncino
    Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:276-281 [Conf]
  41. Mirko Loghi, Massimo Poncino, Luca Benini
    Cycle-accurate power analysis for multiprocessor systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:410-406 [Conf]
  42. Alberto Macii, Enrico Macii, Giuseppe Odasso, Massimo Poncino, Riccardo Scarsi
    Regression-Based Macromodeling for Delay Estimation of Behavioral Components. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:188-191 [Conf]
  43. Enrico Macii, Massimo Poncino
    Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:60-65 [Conf]
  44. Enrico Macii, Massimo Poncino
    Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:112-0 [Conf]
  45. Enrico Macii, Massimo Poncino
    Exact Computation of the Entropy of a Logic Circuit. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:162-167 [Conf]
  46. Enrico Macii, Massimo Poncino, Sabino Salerno
    Combining wire swapping and spacing for low-power deep-submicron buses. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:198-202 [Conf]
  47. Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino
    STV-Cache: a leakage energy-efficient architecture for data caches. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:404-409 [Conf]
  48. Kimish Patel, Enrico Macii, Massimo Poncino
    Zero clustering: an approach to extend zero compression to instruction caches. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:56-59 [Conf]
  49. Olga Golubeva, Mirko Loghi, Massimo Poncino
    On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:489-492 [Conf]
  50. Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:501-504 [Conf]
  51. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Fast power estimation for deterministic input streams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:494-501 [Conf]
  52. Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino
    Parameterized RTL power models for combinational soft macros. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:284-288 [Conf]
  53. Fabrizio Ferrandi, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi, Fabio Somenzi
    Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:235-241 [Conf]
  54. Gary D. Hachtel, Mariano Hermida de la Rica, Abelardo Pardo, Massimo Poncino, Fabio Somenzi
    Re-encoding sequential circuits to reduce power dissipation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:70-73 [Conf]
  55. Kimish Patel, Enrico Macii, Luca Benini, Massimo Poncino
    Reducing cache misses by application-specific re-configurable indexing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:125-130 [Conf]
  56. Massimo Poncino, Jianwen Zhu
    DynamoSim: a trace-based dynamically compiled instruction set simulator. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:131-136 [Conf]
  57. Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino
    Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:494-499 [Conf]
  58. Gianpiero Cabodi, Luciano Lavagno, Enrico Macii, Massimo Poncino, Stefano Quer, Paolo Camurati, Ellen Sentovich
    Enhancing FSM Traversal by Temporary Re-Encoding. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:6-11 [Conf]
  59. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi
    A Structural Approach to State Space Decomposition for Approximate Reachability Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:236-239 [Conf]
  60. Franco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino
    Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:496-501 [Conf]
  61. Mirko Loghi, Luca Benini, Massimo Poncino
    Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:393-396 [Conf]
  62. Andi Nourrachmat, Sabino Salerno, Enrico Macii, Massimo Poncino
    Energy-Efficient Color Approximation for Digital LCD Interfaces. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:81-86 [Conf]
  63. Kimish Patel, Enrico Macii, Massimo Poncino
    Frame Buffer Energy Optimization by Pixel Prediction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:98-101 [Conf]
  64. Antonio Lioy, Massimo Poncino
    On the Resetability of Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1507-1510 [Conf]
  65. Alberto Macii, Enrico Macii, Massimo Poncino
    Increasing the locality of memory access patterns by low-overhead hardware address relocation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:385-388 [Conf]
  66. Sabino Salerno, Enrico Macii, Massimo Poncino
    Crosstalk energy reduction by temporal shielding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:749-752 [Conf]
  67. Kimish Patel, Enrico Macii, Massimo Poncino
    Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:361-364 [Conf]
  68. Luca Benini, Angelo Galati, Alberto Macii, Enrico Macii, Massimo Poncino
    Energy-efficient data scrambling on memory-processor interfaces. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:26-29 [Conf]
  69. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Discharge current steering for battery lifetime optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:118-123 [Conf]
  70. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Selective instruction compression for memory energy reduction in embedded systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:206-211 [Conf]
  71. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer
    System-level power optimization of special purpose applications: the beach solution. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:24-29 [Conf]
  72. Luca Benini, Alberto Macii, Massimo Poncino
    A recursive algorithm for low-power memory partitioning. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:78-83 [Conf]
  73. Luca Macchiarulo, Enrico Macii, Massimo Poncino
    Low-energy for deep-submicron address buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:176-181 [Conf]
  74. Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Stream synthesis for efficient power simulation based on spectral transforms. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:30-35 [Conf]
  75. Sabino Salerno, Alberto Bocca, Enrico Macii, Massimo Poncino
    Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:206-211 [Conf]
  76. Mirko Loghi, Massimo Poncino, Luca Benini
    Synchronization-driven dynamic speed scaling for MPSoCs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:346-349 [Conf]
  77. Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Dynamic thermal clock skew compensation using tunable delay buffers. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:162-167 [Conf]
  78. Roberto Zafalon, Massimo Rossello, Enrico Macii, Massimo Poncino
    Power Macromodeling for a High Quality RT-Level Power Estimation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:59-0 [Conf]
  79. Alessandro Fin, Franco Fummi, Massimo Poncino, Graziano Pravadelli
    A SystemC-based Framework for Properties Incompleteness Evaluation. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:89-94 [Conf]
  80. Crina Anton, Pierluigi Civera, Ionel Colonescu, Enrico Macii, Massimo Poncino, Alessandro Bogliolo
    RTL Estimation of Steering Logic Power. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:36-46 [Conf]
  81. Alessandro Bogliolo, Enrico Macii, Virgil Mihailovici, Massimo Poncino
    Power Models for Semi-autonomous RTL Macros. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:14-23 [Conf]
  82. Maurizio Bruno, Alberto Macii, Massimo Poncino
    A Statistic Power Model for Non-synthetic RTL Operators. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:208-218 [Conf]
  83. Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
    Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:214-224 [Conf]
  84. Ashutosh Chakraborty, Enrico Macii, Massimo Poncino
    Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:297-307 [Conf]
  85. Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino
    Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:466-476 [Conf]
  86. Sabino Salerno, Enrico Macii, Massimo Poncino
    A Low-Power Encoding Scheme for GigaByte Video Interfaces. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:58-68 [Conf]
  87. Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino
    SystemC Cosimulation and Emulation of Multiprocessor SoC Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:4, pp:53-59 [Journal]
  88. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:74-85 [Journal]
  89. Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto, Enrico Macii, Massimo Poncino
    Testing Core-Based Systems: A Symbolic Methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:4, pp:69-77 [Journal]
  90. Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii, Massimo Poncino
    Discharge Current Steering for Battery Lifetime Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:8, pp:985-995 [Journal]
  91. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:8, pp:769-779 [Journal]
  92. Francesco Poletti, Antonio Poggiali, Davide Bertozzi, Luca Benini, Pol Marchal, Mirko Loghi, Massimo Poncino
    Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:5, pp:606-621 [Journal]
  93. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Synthesis of power-managed sequential components based oncomputational kernel extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1118-1131 [Journal]
  94. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    A multilevel engine for fast power simulation of realistic inputstreams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:459-472 [Journal]
  95. Luca Benini, Enrico Macii, Massimo Poncino, Giovanni De Micheli
    Telescopic units: a new paradigm for performance optimization of VLSI designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:220-232 [Journal]
  96. Luca Benini, Alberto Macii, Massimo Poncino, Riccardo Scarsi
    Architectures and synthesis algorithms for power-efficient businterfaces. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:969-980 [Journal]
  97. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi
    Automatic state space decomposition for approximate FSM traversal based on circuit analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1451-1464 [Journal]
  98. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto
    Symbolic optimization of interacting controllers based onredundancy identification and removal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:760-772 [Journal]
  99. Luca Benini, Alberto Macii, Massimo Poncino
    Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:1, pp:5-32 [Journal]
  100. Mirko Loghi, Massimo Poncino, Luca Benini
    Cache coherence tradeoffs in shared-memory MPSoCs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:383-407 [Journal]
  101. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:4, pp:351-375 [Journal]
  102. A. Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1544-1549 [Conf]
  103. Olga Golubeva, Mirko Loghi, Massimo Poncino, Enrico Macii
    Architectural leakage-aware management of partitioned scratchpad memories. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1665-1670 [Conf]
  104. K. Duraisami, Prassanna Sithambaram, A. Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino
    Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1061-1064 [Conf]
  105. Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
    Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  106. A. Nurrachmat, Enrico Macii, Massimo Poncino
    Low-energy pixel approximation for DVI-based LCD interfaces. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  107. Mirko Loghi, Luca Benini, Massimo Poncino
    Power macromodeling of MPSoC message passing primitives. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:4, pp:- [Journal]
  108. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer
    Power optimization of core-based systems by address bus encoding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:554-562 [Journal]
  109. Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Glitch power minimization by selective gate freezing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:287-298 [Journal]
  110. Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino
    Parameterized RTL power models for soft macros. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:880-887 [Journal]
  111. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Discrete-time battery models for system-level low-power design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:630-640 [Journal]
  112. Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Stream synthesis for efficient power simulation based on spectral transforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:3, pp:417-426 [Journal]
  113. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Minimizing memory access energy in embedded systems by selective instruction compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:521-531 [Journal]
  114. Luca Benini, Luca Macchiarulo, Alberto Macii, Massimo Poncino
    Layout-driven memory synthesis for embedded systems-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:96-105 [Journal]
  115. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Scheduling battery usage in mobile systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1136-1143 [Journal]
  116. Kimish Patel, Enrico Macii, Massimo Poncino, Luca Benini
    Energy-Efficient Value Based Selective Refresh for Embedded DRAMS. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:70-79 [Journal]

  117. A Scalable Algorithmic Framework for Row-Based Power-Gating. [Citation Graph (, )][DBLP]


  118. Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. [Citation Graph (, )][DBLP]


  119. Enabling concurrent clock and power gating in an industrial design flow. [Citation Graph (, )][DBLP]


  120. Post-placement temperature reduction techniques. [Citation Graph (, )][DBLP]


  121. Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. [Citation Graph (, )][DBLP]


  122. Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functions. [Citation Graph (, )][DBLP]


  123. Temperature-insensitive synthesis using multi-vt libraries. [Citation Graph (, )][DBLP]


  124. Energy efficiency bounds of pulse-encoded buses. [Citation Graph (, )][DBLP]


  125. Optimal sleep transistor synthesis under timing and area constraints. [Citation Graph (, )][DBLP]


  126. NBTI-aware sleep transistor design for reliable power-gating. [Citation Graph (, )][DBLP]


  127. Using soft-edge flip-flops to compensate NBTI-induced delay degradation. [Citation Graph (, )][DBLP]


  128. Energy-optimal synchronization primitives for single-chip multi-processors. [Citation Graph (, )][DBLP]


  129. Aging effects of leakage optimizations for caches. [Citation Graph (, )][DBLP]


  130. An integrated thermal estimation framework for industrial embedded platforms. [Citation Graph (, )][DBLP]


  131. Thermal-aware floorplanning exploration for 3D multi-core architectures. [Citation Graph (, )][DBLP]


  132. On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. [Citation Graph (, )][DBLP]


  133. Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. [Citation Graph (, )][DBLP]


  134. Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction. [Citation Graph (, )][DBLP]


  135. Timing-driven row-based power gating. [Citation Graph (, )][DBLP]


  136. Locality-driven architectural cache sub-banking for leakage energy reduction. [Citation Graph (, )][DBLP]


  137. NBTI-aware power gating for concurrent leakage and aging optimization. [Citation Graph (, )][DBLP]


  138. Dynamic indexing: concurrent leakage and aging optimization for caches. [Citation Graph (, )][DBLP]


  139. Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. [Citation Graph (, )][DBLP]


  140. On-chip Thermal Modeling Based on SPICE Simulation. [Citation Graph (, )][DBLP]


  141. Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. [Citation Graph (, )][DBLP]


  142. Data-Driven Clock Gating for Digital Filters. [Citation Graph (, )][DBLP]


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