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Publications of Author

1. Panagiotis Manolios, Sudarshan K. Srinivasan
   A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems. [Citation Graph (0, 0)][DBLP]
   CHARME, 2005, pp:363-366 [Conf]
   
2. Roma Kane, Panagiotis Manolios, Sudarshan K. Srinivasan
   Monolithic verification of deep pipelines with collapsed flushing. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:1234-1239 [Conf]
   
3. Panagiotis Manolios, Sudarshan K. Srinivasan
   Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:168-175 [Conf]
   
4. Panagiotis Manolios, Sudarshan K. Srinivasan
   Refinement Maps for Efficient Verification of Processor Models. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:1304-1309 [Conf]
   
5. Panagiotis Manolios, Sudarshan K. Srinivasan
   Verification of executable pipelined machines with bit-level interfaces. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:855-862 [Conf]
   
6. Panagiotis Manolios, Sudarshan K. Srinivasan
   A complete compositional reasoning framework for the efficient verification of pipelined machines. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:863-870 [Conf]
   
7. Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon
   Automatic memory reductions for RTL model verification. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:786-793 [Conf]
   
8. Sudarshan K. Srinivasan, Miroslav N. Velev
   Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2003, pp:65-74 [Conf]
   
9. Panagiotis Manolios, Sudarshan K. Srinivasan
   A computationally ef~cient method based on commitment re~nement maps for verifying pipelined machines. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2005, pp:188-197 [Conf]
   
10. Panagiotis Manolios, Sudarshan K. Srinivasan
    A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures. [Citation Graph (0, 0)][DBLP]
    J. Autom. Reasoning, 2006, v:37, n:1-2, pp:93-116 [Journal]
    
11. Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon
    BAT: The Bit-Level Analysis Tool. [Citation Graph (0, 0)][DBLP]
    CAV, 2007, pp:303-306 [Conf]
    
12. Jun-Cheol Park, Vincent John Mooney III, Sudarshan K. Srinivasan
    Combining data remapping and voltage/frequency scaling of second level memory for energy reduction in embedded systems. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:11, pp:1019-1024 [Journal]