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Viresh Paruthi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Viresh Paruthi, Christian Jacobi 0002, Kai Weber
    Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting. [Citation Graph (0, 0)][DBLP]
    CHARME, 2005, pp:114-128 [Conf]
  2. Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi
    Circuit-based Boolean Reasoning. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:232-237 [Conf]
  3. Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman
    Exploiting suspected redundancy without proving it. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:463-466 [Conf]
  4. Christian Jacobi 0002, Kai Weber, Viresh Paruthi, Jason Baumgartner
    Automatic Formal Verification of Fused-Multiply-Add FPUs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1298-1303 [Conf]
  5. Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman, Andreas Kuehlmann
    Scalable Automated Verification via Expert-System Guided Transformations. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2004, pp:159-173 [Conf]
  6. Viresh Paruthi, Andreas Kuehlmann
    Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:459-464 [Conf]
  7. John M. Ludden, Wolfgang Roesner, Gerry M. Heiling, John R. Reysa, Jonathan R. Jackson, Bing-Lun Chu, Michael L. Behm, Jason Baumgartner, Richard D. Peterson, Jamee Abdulhafiz, William E. Bucy, John H. Klaus, Danny J. Klema, Tien N. Le, F. Danette Lewis, Philip E. Milling, Lawrence A. McConville, Bradley S. Nelson, Viresh Paruthi, Travis W. Pouarz, Audre D. Romonosky, Jeff Stuecheli, Kent D. Thompson, Dave W. Victor, Bruce Wile
    Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:1, pp:53-76 [Journal]
  8. Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai
    Robust Boolean reasoning for equivalence checking and functional property verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1377-1394 [Journal]

  9. Formal verification of correctness and performance of random priority-based arbiters. [Citation Graph (, )][DBLP]

  10. Scalable Sequential Equivalence Checking across Arbitrary Design Transformations . [Citation Graph (, )][DBLP]

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